RF MOSFETs Research Articles

Neural network based time domain modelling of 0.18 μm MOSFETs

AbstractIn this paper a new time domain based neural network model of a 0.18 μm RF MOSFET will be demonstrated. The model consists of only three intrinsic non‐linear current sources, each being modelled by a neural network derived from large signal time domain voltage/current waveform measurements at the intrinsic device terminals. This approach negates the traditional method of multi‐bias S‐parameter measurement providing a fast and accurate method of modelling the transistor under large signal conditions. Full verification of the model will be provided against an 80 μm/0.18 μm MOSFET operating at 2.4 GHz. © 2002 Wiley Periodicals, Inc. Microwave Opt Technol Lett 35: 203–206, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.10558

A simple and accurate method for extracting substrate resistance of RF MOSFETs

In this paper, a simple and accurate method was proposed for extracting substrate resistance of an RF MOSFET, the substrate of which is represented by a single resistor. The extraction results from the measured network parameters are presented for various bias conditions. Excellent agreement between the results of measurements and the model for the extracted substrate resistance was obtained up to 18 GHz. Also, the resistance extracted using the proposed method was shown to give scalable results.

Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model

The improved RF performance of silicon-based technologies over the years and their potential use in telecommunication applications has increased the research in RF modelling of MOS transistors. Especially for analog circuits, accurate RF small signal and large signal transistor models are required. In this paper, we propose an accurate, non-quasi-static, large signal (i.e., nonlinear) RF MOSFET model. Our model consists of a current source and a charge source at the drain terminal and a charge source at the gate terminal. The sources' magnitudes are calculated from the gate-bias and drain-bias dependent elements of the MOSFET equivalent circuit. The MOSFET equivalent circuit elements on itself are extracted from S-parameters at all gate voltages and drain voltages that occur in large signal operation. The accuracy of the equivalent circuit based model is validated by large signal RF measurements using a nonlinear network measurement system. Large signal modelling results using the BSIM3v3 compact model are also presented. Both the equivalent circuit based model and the BSIM3v3 model meet the requirements to describe accurately the RF large signal behaviour of MOS transistors.

MOSFET MODELING AND PARAMETER EXTRACTION FOR RF IC'S

After reviewing the basic concept and general strategies, we have examined a variety of examples of modeling and parameter extraction methods for RF MOSFET's. Modeling and parameter extraction techniques popular in III-V FET modeling were reviewed and recent efforts to model the RF MOSFET and extract the model parameters were examined in light of the differences between the MOSFET and the III-V FET. A very simple and accurate parameter extraction method studied in our laboratory for three-terminal modeling considering charge conservation is also introduced. Our works have two important implications. One is that the consideration for charge conservation is important not only for accurate device modeling and circuit simulation but even more for proper parameter extraction. Another is that one accurate large-signal I-V model is enough to be used for DC, low-frequency analog, as well as RF circuit simulation. Four-terminal modeling based on new equivalent circuits to address the high-frequency effects arising in a MOSFET is very complicated and not practical for CAD applications, even without considering the substrate coupling terms. As a temporary alternative, the macro-modeling approach is examined with various examples.

4H-SiC RF power MOSFETs

A 4H silicon carbide lateral RF MOSFET has been fabricated and characterized for the first time. The improved performance of this device was facilitated by a two-metal-layer process, which optimizes the conflicting requirements of acceptable inversion-layer mobility and low contact resistance. The cut-off frequency of the device with 1-μm gate length was in excess of 7 GHz.

The impact of postbreakdown gate leakage on MOSFET RF performances

When the gate-oxide of a MOSFET breaks down, a leakage path is created between channel and gate. In this work, we demonstrate that a simple leakage current increase model can predict the impact of gate-oxide breakdown on MOSFET performance from dc to microwave frequency. We show that severe reduction in RF performance due to input/output mismatch and a gain reduction can result from gate-oxide breakdown.

A small-signal RF model and its parameter extraction for substrate effects in RF MOSFETs

We propose a physically acceptable small-signal model incorporating substrate effects, in order to eliminate the severe frequency-dependence of the intrinsic drain-source resistance observed from a conventional model of RF Si MOSFETs. This model is based on the substrate network where a parallel RC circuit is connected in series with the drain junction capacitance. It is demonstrated that the substrate effects result in the frequency-dispersion of the effective drain-source resistance and capacitance below 10 GHz. An accurate extraction technique using a simple curve-fit approach is developed to determine substrate parameters directly, and their bulk voltage-dependencies are presented in detail. The validity of this model is partially proved by finding intrinsic parameters exhibiting frequency-independence up to 10 GHz. Better agreement with measured S-parameters is achieved by using the new substrate model rather than the conventional one, verifying the accuracy of the physical model and extraction technique.

High frequency characterization of gate resistance in RF MOSFETs

The gate resistances (R/sub g/) of MOSEETs with various geometries have been characterized at various bias conditions at high frequency (HF). The results show that R/sub g/ decreases when either channel length (L/sub f/) or per-finger-width (W/sub f/) increases before reaching a critical L/sub f/ or W/sub f/, and then starts to increase as L/sub f/ or W/sub f/ continues to increase. The irregular geometry dependence of R/sub g/ is caused by the combined distributed effects in both the gate and channel at HF. Stronger contribution from the distributed channel to the effective R/sub g/ is observed in the saturation region of devices with longer channel length (L/sub f/) at lower gate bias (V/sub gs/). The results show that an optimized design of the per-finger-width is necessary for an rf MOSFET to achieve the lowest effective R/sub g/, which is desirable in rf applications.

Impact of probe-to-pad contact degradation on the high frequency characteristics of RF MOSFETs and guidelines to avoid it

Apparent degradation of the RF characteristics of silicon MOSFETs was observed under normal operating conditions. We show that it was not caused by intrinsic device degradation but originated from a degradation of the contact resistance between probe and bonding pad. Guidelines, not limited to MOSFETs only, are given that enable accurate S-parameter measurements for RF modelling and reliability assessment. © 2001 John Wiley & Sons, Inc. Int J RF and Microwave CAE 11: 114–120, 2001.

On the high-frequency characteristics of substrate resistance in RF MOSFETs

The high-frequency (HF) behavior of substrate components in MOSFETs is studied at different bias conditions for a 0.35 μm BICMOS technology in the frequency range up to 10 GHz. It was found that the observed strong bias dependence of the real part of admittance y/sub 22/, Re{y/sub 22/}, is mainly contributed by the channel conductance. A very weak bias dependence of substrate resistance was found after deembedding the measured y/sub 22/ to remove the influence of channel resistance R/sub ds/ and gate-to-drain capacitance C/sub gd/. The results are key to the understanding and modeling of the HF behavior of MOSFET substrate components for RF IC design.

Improved BSIM3v3 model for RF MOSFET IC simulation

An improved BSIM3v3 RF model including external junction diodes to a conventional substrate network is proposed. This model results in much better agreements with the measured output resistance and capacitance than other published models. The accuracy of the model is also demonstrated by observing good agreement between the measured and modelled S-parameters up to 10 GHz.

A new linearization technique for MOSFET RF amplifier using multiple gated transistors

A simple linearization technique using multiple gated common source transistors is proposed where gate width and gate drive (V/sub gs/-V/sub th/) of each transistor are chosen to compensate for the nonlinear characteristics of the main transistor. To demonstrate the feasibility of this approach, a prototype double-gated RF amplifier using two MOSFETs is implemented and its RF characteristics are compared with those of a single one. The results show that, compared with a conventional single-gate transistor amplifier, the third order intermodulation (IMD/sub 3/) is improved by 6 dB with similar gain, fundamental output power, and DC power consumption. Because the auxiliary transistor is smaller than the main one and biased at subthreshold, adding this does not affect amplifier characteristics appreciably other than the nonlinearity. With further optimization using multiple gated transistors, much better nonlinear performance per power consumption would be expected.

High-frequency dependence of channel noise in short-channel RF MOSFETs

Using a two-dimensional (2-D) Green's function technique, similar to Shockley's impedance field technique, simulation results of the drain i/sub d/ and gate induced i/sub g/ channel noise are presented for an nMOS transistor as a function of frequency. The simulation results show that for frequencies much lower than the cutoff frequency of the transistor f/sub t/ the correlation factor (i.e., i~/sub g~/i~*/sub d~///spl radic/i/sub g//sup -2/i/sub g//sup -2/) between the drain and gate channel noise is equal to approximately 0.4j. For frequencies near the f/sub t/ of the device the correlation factor approximately equals 0.3j. For f/f/sub t//spl sim/0.3, the contribution of the gate induced noise compared to the drain noise was found to be on the order of 1% (i.e., i/sub g//sup -2//i/sub d//sup -2/(f/sub t//f)/sup 2/).

Model for the cutoff frequency in RF MOSFETs

We present a simple analytical model for the drain current dependent cutoff frequency fT in submicron high frequency MOSFET's. The model combines the SPICE MOS3 drain current model and a modified McMacken-Chamberlain model for the current dependent transit time, which allows the description of the I-V characteristics and fT vs. current with the same set of SPICE parameters. The model is verified by comparing simulated results to measured data for 0.6 μm RF MOSFET's fabricated at VTT Electronics. The model explains well the observed behaviour. Furthermore, the comparison indicates that when the channel length is reduced to a half-micron range and below, most of the charging delay is caused by the transit time.

Computer-aided design of an RF MOSFET power amplifier

An RF MOSFET power amplifier is designed using linear and nonlinear analysis programs. It includes nonlinear optimisation within a harmonic-balance program. The amplifier has a nominal output of 15 W over the frequency band 118-175 MHz, using a single MOSFET with LC matching elements. The design procedure is described in detail, including the choice of matching networks and stabilising elements as well as the nonlinear optimisation. A nonlinear equivalent-circuit model is used for the RF power MOSFET, while passive-component models take into account the major parasitic effects. The amplifier is constructed directly from the computer-aided design and evaluated. This computer-aided-design approach takes the initial design to a level where only minimal empirical adjustments may be required. A modified procedure is proposed which reduces modelling errors in a final computer-aided design.

電力形MOS-FETを使用した高周波電力増幅器の負荷変動時における出力/損失特性

電力形MOS-FETを使用した高周波電力増幅器の負荷変動時における出力/損失特性

An RF Class C power amplifier for dielectric heating applications

Details are given of a cascade connected, modular, linear power amplifier operating at 27-12 MHz and suitable for dielectric heating applications. The prototype is capable of delivering 300 Watts and employs RF MOSFETs in two cascaded push-pull power amplifiers. Circuit construction is described and recommendations for higher power performance are given..