Monolithic Integrated Circuit Research Articles

A Monolithic Optoelectronic Integrated Circuit of InP p-i-n/Double HBTs Through Transfer-Printing Fabrication

In this letter, we present a photoreceiver front-end circuit that consists of an InP p-i-n photodetector (PIN PD) on an InP transimpedance amplifier (TIA) with double HBTs (DHBTs), in which the key integrated fabrication route of a transfer-printing (TP) process is introduced. Prior to integration, PDs and TIAs are individually fabricated on their respective wafers. Then, a discrete PD with only active layers is transferred onto the destination on a TIA wafer, thereafter, an on-chip coplanar waveguide connection is integrated. The PIN PD and DHBT TIA exhibit excellent performance, characterized by a responsivity of 0.51 A/W at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.55~\mu \text{m}$ </tex-math></inline-formula> with a bandwidth of 20 GHz and a transimpedance gain of 36 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> with a bandwidth of 27 GHz, respectively. Finally, the monolithically integrated circuit demonstrates a better frequency response by maximally reducing the parasitic effect, with an open clear eye diagram under a 20 Gb/s nonreturn-to-zero pattern, which evidently manifests its ability for ultrahigh-rate data operation. The present work, by employing a TP process, overcomes the issues in integrating discrete optoelectronic devices and proposes a unique approach for monolithic optoelectronic integrated circuit fabrication.

Monolithic Photonic Integrated Circuit Based on Silicon Nitride and Lithium Niobate on Insulator Hybrid Platform

Monolithic Photonic Integrated Circuits In article number 2200121, Yonghui Tian, Guanghui Ren and co-workers experimentally demonstrate a monolithic photonic integrated circuit (PIC) for high-speed data communication application on the thin-film lithium niobate on insulator (LNOI) platform. The proposed PIC shows high data modulation rate of 70 Gbps for single channel and the total data throughput reaches up to 280 Gbps, which opens up new avenues for achieving large-scale monolithic integration on the LNOI platform in future.

Broadband 400 GHz On-Chip Antenna With a Metastructured Ground Plane and Dielectric Resonator

The analysis, modeling, design, simulation, and experimental evaluation of a 400 GHz on-chip antenna is presented, with a novel combination of metastructures, a microstrip patch, a quartz-based dielectric resonator, and a diamond-based antireflex layer—all integrated on a 35 nm InGaAs metamorphic high-electron-mobility transistor (mHEMT) technology. The said combination represents a first-time implementation for all submillimeter-wave-capable semiconductor technologies. Circumventing a substrate-thickness limitation of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.98 \mu \text{m}$ </tex-math></inline-formula> , a state-of-the-art broadband, efficient, and to-the-broadside radiating on-chip antenna solution is realized. It achieves a measured impedance bandwidth of 100 GHz, 25.6%, spanning from 340 to 440 GHz. A consistent pattern bandwidth of 75 GHz is recorded, with an efficiency of 50%–66% and a directivity of up to 10.4 dBi—or 27 dBi, with the utilization of a polypropylene-based dielectric lens. The theoretical analysis of the proposed on-chip antenna is presented, and two modeling approaches are shown and compared. Between the analytical and the 3-D electromagnetic (EM) model, the latter is chosen as it offers greater precision in defining the metastructure unit cell and enables the inclusion of the remaining components of the proposed antenna setup. The measured reflection coefficient and far-field patterns are compared to simulations via the utilized model, and a strong agreement is observed. These far-field patterns are acquired with the on-chip antenna inserted within a broadband 400 GHz transmitter submillimeter-wave monolithic integrated circuit, processed on the 35 nm mHEMT technology.

Real-Time Millimeter-Wave Imaging for Moving Targets Realized in a Sparse Array Based on InP-HBT MMICs

Millimeter-wave (MMW) imaging has been widely studied for applications, such as personnel screening and industrial noninvasive testing; however, real-time MMW imaging with a subcentimeter resolution and a large field of view (FoV) for a fast-moving target has been rarely reported to date. In this article, we present the design of such an imaging system at the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band utilizing the concept of multistatic sparse array. Microwave monolithic integrated circuits based on an InP-heterojunction bipolar transistor (HBT) technology are used for the transmitter and receiver chipsets. With the help of an improved backprojection algorithm and a computation platform based on field-programmable gate arrays, real-time imaging for a target moving as fast as about 10 m/s is demonstrated at a frame rate of over 20 frames/s. The imaging resolution is measured to be better than 6 mm and the FoV can reach over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times 1\,\,\text{m}^{2}$ </tex-math></inline-formula> . Imaging of a moving person with concealed items is carried out to illustrate the system’s capability for personnel screening. To the best of the authors’ knowledge, this is the first real-time MMW sparse array imaging system built upon InP-HBT chipsets.

Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs

As Moore’s law with traditional process node scaling is slowing down, other techniques are required for the advancement of process nodes. In this work, we focus on one such alternative: 3-D physical design of integrated circuits (ICs). While many recent studies have shown the benefits of 3-D IC design on timing and power consumption of circuits, routing in 3-D is solely done with the automatic commercial routers and has not been well studied. In this article, we discuss the various routing scenarios that arise from cell partitioning and the metal layer stack in 3-D. Unlike a 2-D IC, the metal layer configuration in 3-D depends on the orientation in which the dies are bonded together. Due to this, depending on the configuration, cells in one tier tend to use routing layers from the other tier. This is referred to as metal layer (or) routing sharing. This depends on the metal layer stack and the cell partitioning in 3-D, as well as the via pitch used for 3-D connections. By analyzing metal layer sharing in detail, we see that it can help reduce metal layer costs in 3-D as well as improve the power consumption and, in some cases, the maximum achievable performance of the circuits. Overall, the 3-D metal layer cost can decrease by 9% along with an improved power delay product of up to 7.5% just from the routing sharing in monolithic 3-D ICs.

High-Efficiency D-Band Monolithically Integrated GaN SBD-Based Frequency Doubler With High Power Handling Capability

A high-efficiency <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula> -band monolithically integrated GaN frequency doubler based on a pair of antiseries four-anode planar GaN Schottky barrier diodes (SBDs) has been successfully fabricated. Unlike the traditional hybrid integrated circuit technology, the monolithic integrated circuit technology has been used in the design and fabrication of GaN SBD-based frequency doubler circuits to achieve good alignment and low conversion losses. At room temperature, the experiments show that the peak conversion efficiency reaches 17.0% at 115.6 GHz under a continuous wave (CW) driving which is a critical requirement for many practical applications. The efficiency of 17.0% is the highest efficiency of GaN SBD-based multipliers at present under CW driving mode. This monolithically integrated doubler also exhibits a broadband high efficiency characteristic of more than 4.7% (−5.58 dB from 17%) across a 10% band from 109 to 121 GHz. In addition, high CW power handling capability of the proposed frequency doubler is verified. The experiments show that the frequency doubler can endure a maximum CW input power of 0.5 W.

The 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

The 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

The 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

The 23rd IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems

Multilayer GCPW-to-AFSIW Transition for High-Performance Systems on Substrate

This letter presents a transition from a top layer grounded coplanar waveguide (GCPW) to an inner layer air-filled substrate-integrated waveguide (AFSIW). Such type of transition is crucial for the interconnection of top layer surface-mounted radio-frequency integrated circuits (RFICs), toward the integration of complete microwave and millimeter-wave systems taking advantage of the low-cost and high-performance AFSIW technological platform. To fulfill the new space application needs, the proposed transition has been developed in the satellite downlink Ka-band ranging from 27.5 to 31 GHz. The structure is detailed with design guidance. For experimental evaluation, a back-to-back prototype has been fabricated and measured. In the operating frequency range, the proposed transition achieves a simulated and measured insertion loss (IL) as low as 0.135 ± 0.015 dB and 0.3 ± 0.18 dB, respectively.

Harmonic Suppression of a Three-Stage 25–31-GHz GaN MMIC Power Amplifier Using Elliptic Low-Pass Filtering Matching Network

In this letter, the modified elliptic low-pass filtering (LPF) matching network (MN) is proposed for harmonic suppression of a wideband gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) power amplifier (PA) at millimeter-wave (mm-wave). To investigate the effectiveness of the method at mm-wave, a three-stage 25–31-GHz GaN MMIC PA is designed using a commercial 150-nm GaN HEMT foundry process, with a mask area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.5\times2.6$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Simulated results show that the second harmonic of the PA can be effectively suppressed by using the elliptic LPF MN. Experimental results show that the realized MMIC PA achieves a saturated power-added efficiency (PAE) higher than 26.1% from 25 to 31 GHz, with a peak PAE of 31.5% at 29 GHz. The saturated gain and output power are more than 20 and 34 dBm within the band, respectively.

A 66-76 GHz Wide Dynamic Range GaAs Transceiver for Channel Emulator Application.

In this study, we developed a single-channel channel emulator module with an operating frequency covering 66–67 GHz, including a 66–76 GHz wide dynamic range monolithic integrated circuit designed based on 0.1 µm pHEMT GaAs process, a printed circuit board (PCB) power supply bias network, and low-loss ridge microstrip line to WR12 (60–90 GHz) waveguide transition structure. Benefiting from the on-chip multistage band-pass filter integrated at the local oscillator (LO) and radio frequency (RF) ends, the module’s spurious components at the RF port were greatly suppressed, making the module’s output power dynamic range over 50 dB. Due to the frequency-selective filter integrated in the LO chain, each clutter suppression in the LO chain exceeds 40 dBc. Up and down conversion loss of the module is better than 14 dB over the 66–67 GHz band, the measured IF input P1 dB is better than 10 dBm, and the module consumes 129 mA from a 5 V low dropout supply. A low-loss ridged waveguide ladder transition was designed (less than 0.4 dB) so that the output interface of the module is a WR12 waveguide interface, which is convenient for direct connection with an instrument with E-band (60–90 GHz) waveguide interface.

IMS2022 Panel Sessions

The panel sessions at this year’s IEEE International Microwave Symposium (IMS) Week, scheduled during lunches, cover a broad range of topics and events spanning the week. Panel sessions are (co)sponsored by the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, the IEEE Microwave Theory and Techniques Society’s (MTT-S) IMS, and the Automatic Radio Frequency Techniques Group (ARFTG) Microwave Measurement Conference. The various sessions are briefly described.

First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High <inline-formula> <tex-math notation="LaTeX">${f}_{\text {T}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${f}_{\text {max}}$ </tex-math></inline-formula> IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on&#x2013;off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {DD}}$ </tex-math></inline-formula>). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

Microwave Flexible Electronics Directly Transformed from Foundry‐Produced, Multilayered Monolithic Integrated Circuits

AbstractMonolithic microwave integrated circuits hold a dominant position in telecom applications, especially in mobile devices with capabilities for wireless connectivity, due to high and repeatable performance, compact form factor, and low cost. With flexible electronic technologies forming the foundation for a rapidly growing wearable and implantable device segment, the need for flexible microwave electronics with levels of performance that match those of rigid counterparts has increased to unprecedented levels. Here, the fabrication processes for transforming a rigid form of foundry‐produced, multilayered monolithic microwave integrated circuit into a flexible format for amplification of radio frequency signals in the gigahertz level are described. The strategy involves a complete replacement of all rigid materials in the integrated circuit that do not provide any active electronic functionality with a soft, silicone elastomer to yield an overall structure that is mechanically compliant. Experimental studies indicate that the transformation process leads to a flexible silicon‐germanium‐based heterojunction bipolar transistor with a maximum oscillation frequency of 49 GHz and a 24 GHz amplifier with a small‐signal gain of 13.2 dB. This approach has potential uses across a diverse set of microwave devices and circuits, in a manner that could enable wireless connectivity using entirely flexible electronics.

Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies

Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper.

Demonstration of a 2 × 800 Gb/s/wave Coherent Optical Engine Based on an InP Monolithic PIC

We report on the development of a two-channel digital coherent optics (DCO) module, based on a monolithic InP photonic integrated circuit (PIC) transceiver and SiGe application-specific integrated circuit (ASIC), paired with a real-time 7 nm digital signal processing (DSP) ASIC. The high-performance coherent optical engine, which utilizes digital Nyquist subcarriers and probabilistic constellation shaping (PCS) techniques, enables long-haul and ultra-long-haul transmission distances over mixed fiber and amplifier types. This work discusses the performance of a DCO unit operating at multiple data rates over three practical real-world-like network distances. 800 Gb&#x002F;s data transmission over a 1,000 km standard single mode fiber link was achieved using a 96 GBd, PCS-64QAM modulation format. Results of extended reaches of over 2,400 km and 5,000 km are also presented with data rates of 600 Gb&#x002F;s and 400 Gb&#x002F;s, respectively.

Dielectric Coating Deposition Regimes during Electron-Beam Evaporation of Ceramics in the Fore-Vacuum Pressure Range

We present experimental results on the deposition of dielectric coatings on metal surfaces by electron-beam evaporation of alumina ceramics in nitrogen and oxygen gas medium at the pressures of 5–30 Pa. The feasibility of implementing this approach is associated with the use of unique fore-vacuum plasma electron sources. The effect of electron beam power on the rates of ceramic target evaporation and, consequently, on the coating deposition rate is investigated. The structure, electrical-insulating and mechanical (wear resistance, adhesion) properties of the deposited coatings is investigated. We also show the possibility of using coatings for electrical insulating of wires and monolithic integrated circuits.

Wireless Modal Testing With Multiple Battery-Free Backscatter Sensors

This paper reports the design, implementation and the result of real-world experiment of wireless modal testing with battery-free backscatter sensors. The battery-free backscatter sensor comprises a custom radio frequency integrated circuit (RFIC), a commodity micro electro-mechanical system (MEMS) accelerometer, and an antenna. Sensor data concurrency demanded in modal testing is realized by allocating a dedicated subcarrier to each backscatter sensor. The orchestration of wireless communications in 920 MHz based on Gen2 protocol and the wireless power supply to the backscatter sensor are performed by a software defined interrogator built on LabVIEW communications and USRP. We developed an over the air (OTA) subcarrier frequency allocation with a sequence of WRITE commands of Gen2 protocol, and its performance was confirmed with the experiments in an indoor radio propagation. The accuracy of the proposed wireless structural modal testing was experimentally verified by comparing with a commercial modal testing system with wired accelerometers. Wireless modal testing were performed both with sine sweep excitation and random excitation. The experiment reveals that wireless modal testing up to 100 Hz can be successfully performed by battery-free wireless sensors. It is also revealed that the selection of subcarrier bitrate is important to secure the bandwidth of the measurement while preserving a sufficient number of subcarrier channels.

Ultralow-Power Digital Control and Signal Conditioning in GaAs MMIC Core Chip for X-Band AESA Systems

This work presents the design and characterization of an ultralow-power core chip for electronically scanned arrays at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$X$ </tex-math></inline-formula> -band, implemented in 0.25-/0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> E-/D-mode gallium arsenide (GaAs) pHEMT technology. In particular, design details are given about the two core functional blocks embedded in the microwave monolithic integrated circuit (MMIC): a 12-bit phase and amplitude control circuit and an 18-bit serial-to-parallel (S2P) interface. The S2P interface was designed resorting to a custom symmetric device model, expressly conceived for the time-domain simulations required for digital circuits. Due to the adoption of a differential structure with resistive pull-ups, it achieves a state-of-the-art power consumption of 2.2 mW/bit and nearly 87% yield. The analog circuit includes a 6-bit phase shifter (PS) and a 6-bit attenuator. To mitigate risks, two different PS architectures have been developed and are compared in this work, discussing advantages and drawbacks of the different solutions. Since the two designs share the same target specifications, a truly fair comparison can be made not only in terms of performance but also concerning robustness and repeatability, thus providing useful guidelines for the selection of the most appropriate strategy. In particular, it is shown that one architecture outperforms the other by about 2 dB and 1.5° in terms of insertion loss and rms phase error, respectively.

Collector Series-Resistor to Stabilize a Broadband 400 GHz Common-Base Amplifier

The indium phosphide (InP) 130 nm double-heterojunction bipolar transistor (DHBT) offers milliwatts of output power and high signal amplification in the lower end of the terahertz frequency band when the transistor is used in a common-base configuration. Instrumentation can directly benefit from this technology by enabling the development of novel broadband sources or synthesizers that rely on our ability to amplify the signal over enormous bandwidths. However, the design of high gain and stable amplifiers presents many obstacles and limitations as we increase the bandwidth and the carrier frequency. Here, we show that adding a series resistor at the collector terminal of the common-base transistor prevents instabilities in the terahertz monolithic integrated circuit amplifier and increases its fractional bandwidth. Adopting this technique, we report a state-of-the-art broadband common-base amplifier that exhibits a minimum small-signal gain of 18.9 dB from 325 to 477 GHz. This amplifier presents the highest fractional bandwidth and gain above 300 GHz. Our work demonstrates the feasibility of high-performance amplifiers that address the need of future terahertz electronic systems.