Reversible Logic Research Articles

Reversible Computations of One-Way Counter Automata

Deterministic one-way time-bounded multi-counter automata are studied with respect to their ability to perform reversible computations, which means that the automata are also backward deterministic and, thus, are able to uniquely step the computation back and forth. We study the computational capacity of such devices and obtain separation results between irreversible and reversible k-counter automata for polynomial and superpolynomial time. For polynomial time and exponential time we obtain moreover infinite and tight hierarchies with respect to the number of counters. These hierarchies are shown with Kolmogorov complexity and incompressibility arguments. In this way, on passing we can prove these hierarchies also for ordinary counter automata. This improves the known hierarchies for ordinary counter automata in the sense that we consider here a weaker acceptance condition. Then, it turns out that k +1 reversible counters are not better than k ordinary counters and vice versa. Finally, almost all usually studied decidability questions turn out to be undecidable and not even semidecidable for reversible multi-counter automata, if at least two counters are provided. In case of reversible one-counter automata, it is possible to show that the inclusion problem is also not even semidecidable.

The Complexity of Iterated Reversible Computation

We study a class of functional problems reducible to computing $f^{(n)}(x)$ for inputs $n$ and $x$, where $f$ is a polynomial-time bijection. As we prove, the definition is robust against variations in the type of reduction used in its definition, and in whether we require $f$ to have a polynomial-time inverse or to be computible by a reversible logic circuit. These problems are characterized by the complexity class $\mathsf{FP}^{\mathsf{PSPACE}}$, and include natural $\mathsf{FP}^{\mathsf{PSPACE}}$-complete problems in circuit complexity, cellular automata, graph algorithms, and the dynamical systems described by piecewise-linear transformations.

Compact hybrid silicon nitride and lithium niobate nano-film photoelectronic reversible logic gate

Photoelectronic hybrid logic operation improves digit circuit efficiency without any additional photoelectric conversion, especially a photoelectronic reversible logic gate may reduce energy dissipation. In this paper, a compact photoelectronic reversible logic gate is proposed based on a hybrid silicon nitride and lithium niobate nano-film waveguide. Tow Mach-Zehnder modulators are cascaded together to construct the main part of the compact photoelectronic reversible logic gate. The whole length of the gate is only 4.4mm, one hundredth of the length of the common proton exchange lithium niobate modulator. By operating at the wavelength of 1.55μm, the proposed Mach-Zehnder modulator only requires 4.9V voltage to complete a full cross-coupling, which is well compatible with CMOS technology. It is demonstrated that at the wavelength range of 1.4μm to 1.6μm, the average insertion loss is 0.6dB, the minimum crosstalk is -47dB, and the maximum extinction ratio is 41dB; in the voltage range of 4V to 6V, the average insertion loss is 0.63dB, the minimum crosstalk is -26dB, and the maximum extinction ratio is 22dB. These features indicate that the photoelectronic reversible logic gates have good performances, bringing the photoelectronic logic gates into a new design parameter space and providing a possible solution for easing the electronic bottleneck.

A novel re-entry trajectory design strategy enforcing inequality and terminal constraints in height-velocity plane

A novel re-entry trajectory design approach for a winged reusable launch vehicle that satisfies path and terminal state constraints in the height velocity plane is proposed in this paper. A two-phase re-entry trajectory is proposed. A height-velocity plane entry corridor is designed using all path and quasi-equilibrium glide constraints. The proposed method creates the reference trajectory inside the re-entry corridor using three piecewise polynomials, such as linear and logarithmic. A two-parameter search optimization problem minimizes terminal range-to-go error for this reference trajectory generation problem. Improved Search Space Reduction solves this optimization problem. The Improved Search Space Reduction algorithm is compared to the Grey Wolf Optimizer and Particle Swarm Optimisation algorithms to prove its efficacy and superiority. The reference bank angle is modified using feedback linearization and bank reversal logic to create an entry trajectory that meets all path and terminal constraints. The effectiveness of the proposed method has been validated through Monte Carlo simulations that incorporate uncertainties such as variations in initial state, uncertainties in aerodynamics, and atmospheric perturbations. The controller OPAL-RT OP4510 provides bank angle command at every instant based on the current state of the vehicle parameters associated with real-time simulator OP4510. The real-time hardware-in-loop simulation results show that the obtained re-entry trajectory satisfies all path and terminal constraints.

Design and Optimization of Reversible Arithmetic Unit Using Modified Gate Diffusion Input Logic

ABSTRACTIncreasing integration levels and demand for portability have made minimising the power consumption of circuits increasingly important for wide range of applications. Reversible logic is a low-power, low-loss design that can be utilised in low power CMOS, optical computing, nanotechnology, and quantum computing. Quantum machine learning Research is an area examines combining ideas from quantum computing and machine learning. In this paper, a new design of reversible logic-based arithmetic unit is demonstrated with CMOS and modified-GDI (MGDI) methodology for nanoscales using reversible gates. We provide a design for an optimized arithmetic unit, as well as some proposed methodologies for designing a reversible arithmetic unit with novel reversible gates, and compare them to existing circuits in terms of garbage output, constant input, number of reversible gates, and quantum cost, in this work. It can also be employed in Quantum computers due to its lower Quantum Cost and Garbage Output. Transistor-level implementations of the proposed arithmetic units are accomplished using Cadence Virtuoso tool GPDK 90 nm technology in combination with CMOS and MGDI techniques. Due to the optimization, the proposed arithmetic unit shows better performance in worst-case delay and power consumption than a comparable non-optimized Arithmetic Unit. According to the design and analysis of proposed Arithmetic Units. The proposed −1 design of the 4-bit Arithmetic Unit achieves optimisation by incorporating a reduced number of reversible gates and exhibiting a low quantum cost (12&40) using MGDI-FS. Similarly, the proposed −2 and 3 designs minimizes the number of transistors required, with a count of 80 and 120, and proposed −3 design, it eliminates the presence of constant inputs entirely using MGDI-FS.

Utilizing a Novel Universal Quantum Gate in the Design of Fault-Tolerant Architecture

In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and reversible circuits have control error problems. The advantage of a quantum gate-based architecture is that it prevents heat loss, and it has been extensively researched. In this article, we have developed reversible multiplexers (mux's), half-adder (HA), and full-adder (FA) and latches that are fault-tolerant by making use of new gate and implementing them on the IBM Qiskit platform. A power-efficient and fault-tolerant mux's and latches is proposed that uses reversible gates to preserve parity. Multiplexer kinds such as 2:1, 4:1, and n:1 is covered in depth by the new Parity Preserving Multiplexer (PPM) gate and verified by IBM-Qiskit. An algorithmic design for an n:1 multiplexer is invented. In order to assess a PPM gate effectiveness, 13 standard Boolean functions and 8 standard types of gates are implemented. The PPM quantum gate is built using quantum assembly code (QAC), which runs on IBM Quantum Lab and IBM Quantum Composer platforms to measure the output qubits. Additional HA, muxes, and latches design led to the code creation in the Qiskit platform, which was used to measure the output qubits. A comparison of the D-latch, T-latch, JK-latch, and mux designs with existing circuits shows a reduction in quantum cost (qc) and junk output (go) and the implementation of a custom design in the IBM-Qiskit platform to measure output qubits is a first time in literature.

Universal and Reversible Gate Design in Quantum-dot Cellular Automata Nanotechnology

Background: Growing progress in the field of nanoelectronics necessitates ever more advanced nanotechnology due to the continued scaling of conventional devices. For the purpose of fabricating current integrated circuits (ICs), Quantum-dot cellular automata (QCA) nanotechnology is the most suitable substitute for complementary metal oxide semiconductor (CMOS) technology. The problem of short-channel secondary effects at the ultra-nanoscale level confronts CMOS technology Aims: QCA nanotechnology overcomes the issues of conventional logic circuit design methods due to its numerous advantages. This research work aims to design an energy-efficient, reliable, universal, 3×3, and reversible logic gate for the implementation of various logical and Boolean functions in QCA nanotechnology. Objective: It is desirable for portable systems to have a small size, extremely low power consumption, and a clock rate in the terahertz. As a result, QCA nanotechnology is an incredible advancement for digital system applications and the design of future systems. Methods: This research article proposes a novel, ultra-efficient, multi-operative, 3×3 universal reversible gate implemented in QCA nanotechnology using precise QCA cell interaction. The proposed gate is used for the implementation of all the basic logic gates to validate its universality. The implementation of all thirteen standard Boolean functions establishes the proposed gate's multi-operational nature. The energy dissipation analysis of the design has been presented for the varying setups. Results: The proposed gate is area-efficient because it uses minimum QCA cells. Various logical and Boolean functions are effectively implemented using the proposed gate. The result analysis establishes the minimum energy dissipation of the proposed design and endorses it as an ultra-efficient design. Conclusion: The QCA cell interaction method demonstrates the best way to design a universal, reversible, and multi-operative gate.

Design‐for‐testability for reversible logic circuits based on bit‐swapping

AbstractThe emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low‐power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k‐CNOT), k ≥ 1. While analysing testability issues in a reversible circuit, the missing‐gate fault model is often used for modelling physical defects in k‐CNOT gates. A new design‐for‐testability (DFT) technique is proposed for reversible circuits that deploys bit‐swapping using Fredkin reversible gates. It is shown that in an (n × n) circuit implemented with k‐CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of maximum size 2n + 1 that detects all detectable missing gate faults in the original circuit, where n is the number of input/output lines in the circuit. The DFT overhead in terms of quantum cost is much less compared to that of previous approaches. The method is more advantageous for large circuits.

Review on Reversible Logic Gates

Abstract: Reversible logic gates have emerged as a pivotal area of research in the field of digital circuit design, offering the promise of ultra-low power consumption. This survey paper comprehensively explores the foundations and practical applications of reversible logic gates. Beginning with an introduction to the fundamental principles of reversibility, it delves into the design of reversible gates, covering CNOT, Feynman, Toffoli, Peres, Fredkin gates, and beyond. The paper offers a systematic review of state-of-the-art research in the field, discussing various optimization techniques and quantum-inspired reversible circuits. It also investigates real-world applications, ranging from low-power VLSI design to quantum computing. By summarizing the key findings, challenges, and potential future directions in reversible logic gate design, this survey paper provides a valuable resource for researchers, engineers, and enthusiasts seeking a comprehensive understanding of this transformative technology

The monoidal nature of the Feistel-Toffoli construction

The Feistel-Toffoli construction of a bijective Boolean function out of an arbitrary one, a fundamental tool in reversible computing and in cryptography, has recently been analyzed (see [12]) to be a special instance of the construction of a monoid homomorphism from the X -fold cartesian power of a monoid M into the endomorphism monoid of the free M -set over the set X . It is the purpose of this note to show that this construction itself is in fact a genuine monoidal one. The generalization of the Feistel-Toffoli construction to internal categories in arbitrary finitely complete categories of [12] then becomes a special instance of this monoidal description.

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

Certifying expressive power and algorithms of reversible primitive permutations with Lean

Reversible primitive permutations (RPP) is a class of recursive functions that models reversible computation. We present a proof, which has been verified using the proof-assistant Lean, that demonstrates RPP can encode every primitive recursive function (PRF-completeness) and that each RPP can be encoded as a primitive recursive function (PRF-soundness). Our proof of PRF-completeness is simpler and fixes some errors in the original proof, while also introducing a new reversible iteration scheme for RPP. By keeping the formalization and semi-automatic proofs simple, we are able to identify a single programming pattern that can generate a set of reversible algorithms within RPP: Cantor pairing, integer division quotient/remainder, and truncated square root. Finally, Lean source code is available for experiments on reversible computation whose properties can be certified.

Fault modeling for external energy or internal cell defect in quantum dot cellular automata

Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.

Classical half-adder using trapped-ion quantum bits: Toward energy-efficient computation

Reversible computation has been proposed as a future paradigm for energy efficient computation, but so far few implementations have been realized in practice. Quantum circuits, running on quantum computers, are one construct known to be reversible. In this work, we provide a proof-of-principle of classical logical gates running on quantum technologies. In particular, we propose and realize experimentally, Toffoli and Half-Adder circuits suitable for classical computation, using radio frequency-controlled 171Yb+ ions in a macroscopic linear Paul-trap as qubits. We analyze the energy required to operate the logic gates, both theoretically and experimentally, with a focus on the control energy. We identify bottlenecks and possible improvements in future platforms for energetically efficient computation, e.g., trap chips with integrated antennas and cavity qed. Our experimentally verified energetic model also fills a gap in the literature of the energetics of quantum information and outlines the path for its detailed study, as well as its potential applications to classical computing.

An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm

Atomic silicon and reversible logic are domain field-coupled nanocomputing (FCN) techniques that have drawn significant attention for their lower power consumption, area, and design overhead. As atomic silicon and reversible logic reach dramatically reduced occupied area and power consumption, they can be a suitable alternative to CMOS technology. These technologies can significantly reduce the occupied area and energy consumption in all kinds of digital circuits, which are the two most challenging aspects of developing digital circuits. On the other hand, the Miller algorithm is a crucial synthesis for suggesting reversible circuits with extraordinary techniques in nanotechnology. It is an exceptionally effective and systematic method based on quantum rules for designing and proposing reversible circuits that can help suggest a reversible gate with low energy and a low occupied area. This study aims to construct novel nano-scale circuits with a focus on low-occupied area and minimal energy consumption as essential factors while designing digital circuits. In this paper, we propose a reversible gate with the well-known Miller algorithm and atomic silicon technology. Then it is used to develop a reversible full adder, 4-bit ripple carry adder, and 4:2 compressor. Finally, the proposed structures are simulated using the SiQAD tool.

High-efficient reversible full adder realized by dynamic threshold-based gate diffusion input logics

A new 12-transistor reversible full adder (FA) is designed based on carbon-nanotube-field effect transistors (CNTFETs) with 32 nm channel length and an area of 0.2204 μm2, 1 constant input (CI), and 3 garbage outputs (GO). The FA has 3 reversible logic gates in two of its stages that are realized by the gate diffusion input (GDI) technique. In the FA, 2 Toffoli gates with 1 CI and 1 new GDI-reversible-multiplexer are used to generate Sum and Cout, respectively. The multiplexer is 3*3, with two GOs, and a significant area reduction by only two transistors. The inputs of the circuit prevent the excessive increase of GOs and CIs. The Monte Carlo analysis using the HSPICE simulator indicates a better sensitivity of the FA versus fabrication with 6.45%, 1.86%, and 8.01% improvements of maximum values of power, delay, and power-delay-product (PDP). The FA is implemented in a 4-bit, 8-bit, 16-bit, and 32-bit ripple carry adder (RCA), and its superior results are seen. Under 32-bit RCA, the proposed circuit with 4956.30 fJ shows more energy savings compared to most competitors. The extracted results, the different figure of merits (FoMs), and reversibility features represent the proposed circuit as a desirable procedure for future works.

Empowering energy with a cutting-edge reversible logic framework for universal shift registers

In order to meet the increasing need for reduced power consumption, reduced circuit size, and increased operating speed, this research focuses on the efficient design of reversible shift registers. The shift register is an essential building block of both arithmetic logic units (ALUs) and reversible memory circuits. In this research, an improved layout is shown for a variety of shift register types, including those with serial input and parallel output (SIPO), serial input and serial output (SISO), parallel input and parallel output (PIPO), parallel input and serial output (PISO), and universal shift registers (USR). Our approaches lessen waste in compared to standard procedures by maximizing '0′ GO and reducing CI. The 4-bit SIPO register has a 70 % increase in CI performance over previous designs and also provides SISO capability with a 50 % CI and 100 % GO boost. Our proposed designs for the SIPO, SISO, PIPO, and PISO registers also result in a 70 % and 80 % improvement in CI and GO for the 4-bit PISO register. We enhance the 4-bit Universal Shift Register (USR) design by 62.5 % in CI, 50 % in CI, 12.5 % in GO, and 56.25 in GO over the previous design.

All-optical photonic crystal Feynman and NOT logic gates based on the interference effect

In this paper, an ultra-compact photonic crystal structure for the development of reversible Feynman and NOT logic gates is introduced. The proposed structure includes two-dimensional (2D) silicon dielectric rods in air. The analysis and evaluations are carried out using finite-difference time-domain (FDTD) and plane-wave expansion (PWE) methods. The proposed design provides a smaller structure, higher contrast ratio, lower power consumption, and compatibility with silicon technology. In the application of this structure for a NOT logic gate, one port is considered as control with a contrast ratio of 28.73 dB between 0 and 1 logic levels. For the Feynman logic gate, the contrast ratio is 20.33 dB. Moreover, the response times for the proposed Feynman and NOT logic gates are 0.54 ps and 0.56 ps, respectively. High optical output power, small dimension, and low response time make our proposed structure a suitable candidate for all-optical integrated circuits.

A Novel Spin Based Logic Circuitry Synthesis Using SS Gate

Abstract: Because of its perceived advantages, reversible logic has attracted a lot of study attention. It introduces commendable characteristics like low power consumption, minimized garbage output, and least propagation delay. Reversible logic integrated circuits (ICs) have been produced utilizing traditional CMOS topology in a number of published research endeavors up to this point. However, because CMOS technology is already experiencing a common scaling down issue, researchers are now focusing on post-CMOS devices for the manufacturing of reversible integrated circuits in the future. This particular research project is focused on related research projects that feature reversible IC design based on Spintronic. The authors first implemented spinoriented conventional reversible logic gates and evaluated their effectiveness in terms of generated garbage values, power consumption, device integrity, and size. Later, in order to understand the benefits of the suggested Single Spin Logic based SS gate, the authors come across an SS gate that is singular in its kind and stick to its spin realization.

Design of Multiplexers using Reversible Logic Technique

Reversible logic is promising as it can be applied to different applications in low power like nanocomputing especially in quantum computing. Reversible logic is a technioue for power reduction. Reversible circuits are similar to digital circuits but they work using reversible logic gates. This study focuses on reducing the garbage output and ancilla inputs in reversible multiplexers, thereby reducing the power consumption. In this study two designs of Multiplexers are given. Design1 is using TwinSJ gate and AJ gate. 2:1, 4:1 and 8:1 multiplexers are built. In Design 2, a new gate (SJ gate) is built which functions as 2:1 multiplexer. It has 4*4 configuration. The inputs are suitably configured so that it performs various logic functions. Using this SJ gate and other basic reversible logic gates, 2:1, 4:1 and 8:1 multiplexers are built. In 2:1 multiplexer, Ancilla inputs are improved to '0' from 5 and garbage output has been reduced to 2 against 7 in existing design. 4:1 multiplexers are built with ‘0’ ancilla inputs against 2 and 11 in existing designs. Garbage output of the proposed 4:1 multiplexer is 5 against 6 and 16 in existing designs. 8:1 multiplexer is built with 1 ancilla input and 11 garbage output against 2 and 12 respectively in existing design. This is designed using VHDL code - xilinx 14.7 for verification purpose and simulated on ISIM.