Reversible Logic Research Articles

Implementation of Quantum Image Encryption via Reversible Quantum Logic Gates Computing

With the development of quantum communication technology, Shor’s algorithm is expected to crack RSA encryption. Quantum communication will change the method of classical encryption in the future. We propose a quantum image encryption method via reversible quantum logic gates computing as quantum computing is reversible. An entangled pair of qubits are used for data transmission. The plaintext image is encrypted into an encrypted image via the quantum gate by using superdense coding to encrypt and transmit the operating quantum gate. The encrypted image is decoded by reversible computing, which is expected to provide a way for quantum image encryption.

Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing

Nowadays, quantum computing plays a significant role in reducing the execution time in complicated computations. There are different reversible algorithms for quantum computation and many quantum circuits theoretically designed until now. These designs are only built from reversible gates because reversibility is a necessary logic in quantum circuits. Additionally, ternary representation can allow designing a circuit with fewer inputs and outputs, leading to a considerable decline in size or number of qutrits. Although other papers in quantum ternary reversible logic are in unbalanced representation, this paper, for the first time, considers balanced ternary advantages to achieve a more efficient design for quantum multipliers as the main component in arithmetic blocks. Six criteria are introduced to show how balanced representation increases the overall performance. In this work, two general balanced ternary adder blocks (full-adder and half-adder) and two balanced ternary partial product generators (BTPPGs) are proposed, and also a 2 × 2 and a 3 × 3 balanced ternary multipliers built from these components. The quantum costs of proposed balanced ternary multipliers enhanced 17% for a 2 × 2 multiplier and 34% for a 3 × 3 multiplier.

MF-RALU: design of an efficient multi-functional reversible arithmetic and logic unit for processor design on the field programmable gate array platform

Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a <11% chip area and consumes 332 mW total power. The RISC processor utilizes a <3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA.

Measurements of variable capacitance using single port radio frequency reflectometry

A radio frequency (RF) reflectometry technique is presented to measure device capacitances using a probe station. This technique is used to characterize micro-electromechanical system (MEMS) variable capacitor devices that can be connected to create pull-up and pull-down networks used in digital gates for reversible computing. Adiabatic reversible computing is a promising approach to energy-efficient computing that can dramatically reduce heat dissipation by switching circuits at speeds below their RC time constants, introducing a trade-off between energy and speed. The variable capacitors in this study will be measured using single port RF reflectometry achieved with a custom-made RF probe. The RF probe consists of a micromanipulator with an on-board matching network and is calibrated by measuring a capacitive bank that shows a clearly visible frequency shift with the increase in capacitance. The RF probe worked well when measuring static capacitors with no parasitic resistance; however, the frequency shift is masked when measuring the MEMS variable capacitors due to their high in-series parasitic resistance (around 80 kΩ). Therefore, RF reflectometry has the potential to measure MEMS variable capacitors in the range of 0–30 fF when not masked by a high in-series parasitic resistance, creating a fast and versatile method for characterizing variable capacitors that can be used in energy-efficient computing.

Optimization of Adiabatic Superconducting Logic Cells by Using π Josephson Junctions

Adiabatic superconducting logic circuits can ensure the practical implementation of operations with the energy dissipation below the Landauer limit. However, applications of the existing solutions are limited because of two contradictory requirements of a high energy efficiency and a sufficiently fast response of devices. Josephson junctions with a negative critical current (π junctions) allow one to obtain a certain form of the potential energy of superconducting circuits and, as a result, a practically required degree of control of dynamic processes in the proposed reversible logic cells. The features of the current transport and balance of Josephson phases in circuits with π junctions make it possible to improve the coupling between the parts of a reversible computer by a factor more than 2. At the same time, the continuous evolution of the state is ensured at higher critical currents and higher characteristic voltages of the main Josephson junctions of adiabatic superconducting logic cells, which allows an increase in the response rate.

Two Circuits for Directing and Controlling Ballistic Fluxons

Reversible logic schemes using flux solitons (fluxons) on long Josephson junctions (LJJs) have recently been proposed. The attraction of the fluxon is that it propagates ballistically along an LJJ until it encounters a change in the character of the LJJ, often a designed circuit element. Logic gates involve fluxons interacting with circuit elements and with other fluxons. However, testing of ballistic fluxon circuits requires other circuits outside the logic family to direct and control fluxon motion. We discuss two such <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">non-reversible</i> fluxon control circuits. First, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">polarity filter gate</i> is a simple non-reversible gate that allows one polarity of fluxon to pass, while reflecting the other polarity. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</i> state both polarities reflect. Second, the polarity separator generalizes on the polarity filter concept and allows separation of the two fluxon polarities into different LJJs. We discuss simulations of these structures and possible applications.

Equivalent Transformations of Complex Circuits in Calculations of Power Supply Systems of Agrocomplex

he tasks at the stage of planning and operation of power supply systems are related to the calculation of the parameters of their operation modes. With the massive nature of such complex calculations, their execution is possible only with the help of appropriate software and computing tools, that is, using an electronic computer. (Research purpose) The research purpose is to substantiate the algorithm of equivalence of power supply systems or their individual sections as an integral part of the algorithms complex for calculating electrical systems. (Materials and methods) It has been shown that at present there are many agricultural consumers, interruptions in the power supply of which lead to significant damage, in this regard, closed power supply systems are becoming increasingly used, as the requirements for reliability, uninterrupted power supply and the quality of electricity supplied to the consumer are increasing. It was determined that the calculation of closed systems is more complicated than open ones. It was revealed that when solving a wide range of tasks related to the creation and modernization of power supply systems, there is a need to simplify the systems or their individual sections. (Results and discussion) The equivalence rule was formed and methods for calculating equivalent resistances and electromotive force of the converted sections of the replacement circuits were given, which simplifies the circuit and accelerates the process of calculating and analyzing the modes of power supply systems. (Conclusions) It was established that the proposed equivalence algorithm is based on universal formulas for calculating intrinsic and mutual resistances, which were previously obtained by the authors for use in problems of calculating steady-state modes of power supply systems. It was stated that the calculation algorithm is also applicable for the equivalence of forward and reverse sequence circuits in the calculation of currents of asymmetric short circuits and in the analysis of the dynamic stability of electric power systems

Solving the Kemeny ranking aggregation problem with quantum optimization algorithms

The aim of a ranking aggregation problem is to combine several rankings into a single one that best represents them. A common method for solving this problem is due to Kemeny and selects as the aggregated ranking the one that minimizes the sum of the Kendall distances to the rankings to be aggregated. Unfortunately, the identification of the said ranking—called the Kemeny ranking—is known to be a computationally expensive task. In this paper, we study different ways of computing the Kemeny ranking with quantum optimization algorithms, and in particular, we provide some alternative formulations for the search for the Kemeny ranking as an optimization problem. To the best of our knowledge, this is the first time that this problem is addressed with quantum techniques. We propose four different ways of formulating the problem, one novel to this work. Two different quantum optimization algorithms—Quantum Approximate Optimization Algorithm and Quantum Adiabatic Computing—are used to evaluate each of the different formulations. The experimental results show that the choice of the formulation plays a big role on the performance of the quantum optimization algorithms.

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Implementation of the Toffoli and Peres reversible logic gates using magnetic skyrmions in operational gates

Micromagnetic simulations have been used to create reversible logic gates that utilize magnetic skyrmions as input and output signals. The geometrical design of the logic devices consists of a two-dimensional assembly of ferromagnetic nanotracks, resembling rectangular grooves. Drawing an analogy to the billiard-ball model, this study takes into account elastic collisions between magnetic skyrmions and introduces the concept of control skyrmion. The application of spin-polarized currents to the system induces the motion of magnetic skyrmions along the nanotracks. The synchronized movement of magnetic skyrmions across the operational logic gates, required for their interaction, is achieved by incorporating multiple triangular magnetic notches along the nanotracks. Short polarized current pulses are then applied through the logic gates to facilitate this process. We have successfully implemented the XOR/AND and Full Adder logic gates as well as the reversible Toffoli and Peres logic gates using skyrmion-based architectures for computing. Our results offer valuable guidelines for leveraging magnetic skyrmions as digital signals in skyrmion-based computing systems.

A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots

A nano-scale arithmetic and logic unit using a reversible logic and quantum-dots

Konsep Pembelajaran Matematika Sekolah Dasar Berlandaskan Teori Kognitif Jean Piaget

This study aims to explain the concept of learning mathematics in elementary schools based on Jean Piaget's cognitive theory. The focus of this research is how the concept of learning mathematics at the elementary school level is based on Jean Piaget's cognitive theory. This study used a qualitative approach with a library survey data collection method. The data analysis carried out in this study is a form of data analysis using the Miles and Huberman model with three stages of data analysis. From the results of this study it was found that elementary school students are children aged 7 to 12 years who are in the concrete action stage, and they understand reversible and conservative logic operations in the concrete action stage.

Reversible Logic based Cryptography Design Algorithm using Random Keys

Reversible computations, besides quantum computing, have various applications in digital signal processing, nanotechnology and bioinformatics. They are particularly useful in designing low-power devices and improving computational efficiency. Cryptography is vital for protecting sensitive information in fields such as bioinformatics and digital signal processing where private data is frequently exchanged. However, cryptographic algorithms can consume significant power and require large areas, particularly when implemented in hardware. Reversible logic gates offer a potential solution by being more power-efficient and potentially reducing implementation area. Using random numbers as keys for both encryption and decryption in a reversible logic gate-based cryptographic algorithm can enhance security. LSB watermarking is a technique to embed additional metadata into digital media, improving data security. To evaluate the performance of the Field Programmable Gate Array for the Reversible Logic Gate Cryptography Design architecture, comparing it to the other state-of-the-art approach is necessary.

A Genetic Algorithm (GA) and Swarm-Based Binary Decision Diagram (BDD) Reordering Optimizer Reinforced With Recent Operators

The use of Binary Decision Diagrams (BDDs) has proliferated in numerous fields. When a system criterion is formulated in form of a Boolean function, its BDD is constructed. Each node in the BDD is further mapped into another form to be exploited in the system analysis. However, the cost of the resultant mapping form is directly related to the BDD size which can be effectively reduced through applying proper variable reordering followed by applying reduction rules that preserve the fidelity of the BDD in correctly representing the input Boolean function. Although several algorithms have been proposed in the literature to find the optimal order of variables in the BDD, the scalability of such algorithms is a serious barrier when it comes to complex systems with exponential explosion in the possible number of orders in the search space. Furthermore, solely exploring the search space in BDD reordering is not sufficient since better permutations might be obtained with slight tuning of the candidate solutions. Thus, a sufficient degree of equilibrium between exploration and exploitation should be preserved during the evolution of the reordering algorithm. In this paper, we propose a BDD optimizer driven by either Genetic Algorithm (GA) or swarm engines. The proposed GA-based BDD reordering optimizer iteratively processes an essentially large population with a randomized mixing of low destructive crossover/mutation operators. The proposed swarm-based optimizer, on the other hand, maps a vector of real numbers into a permutation to further construct its companion BDD. The generation of the next vector is guided by recent parameter and parameter-less swarm algorithms that are armed with effective mechanisms to simultaneously conduct exploration and exploitation. Experimental results show that our proposed optimizer effectively reduces the resultant BDD size for input Boolean functions with almost linear computational complexity. Furthermore, it has been found that exploiting recent swarm optimizers with spiral movement in BDD reordering problem can outperform GA for large scale Boolean functions. Finally, as a real-world application, our proposed algorithm is applied to reversible logic synthesis to show the achieved reduction in the Quantum Cost (QC) associated with BDD-based synthesis.

Lateral Entry Guidance With Terminal Time Constraint

A simultaneous attack mission requires the entry vehicle to be capable of controlling the terminal time. To satisfy the terminal time constraint and meanwhile to cooperate with the previous longitudinal guidance algorithms, a lateral entry guidance method is developed using a closed-loop trajectory predictor for the terminal time, a bank reversal logic based on a double-corridor strategy, and a terminal time determination approach. The double-corridor contains a time error corridor used to activate the modification of the terminal time, and an adjustable heading corridor, when activated, used to reduce the terminal time error. The desired terminal time is calculated according to a feasibility index which describes the tolerance of aerodynamic dispersions. The simulations of a time constrained entry flight show that the lateral guidance method can achieve a high accuracy of the terminal time control while satisfying the conventional entry constraints. The advantage of the desired terminal time given by the feasibility index is also demonstrated.

Fault-tolerant reversible logic gate-based RO-PUF design

Physically Unclonable Function (PUF) is an emerging modern approach to the security concerns of the physical systems which require the protection of sensitive data. PUF generates unique, reliable, and secure responses which can be utilized for cryptographic applications. In this paper, a fault-tolerant reversible logic gate-based RO PUF is proposed. We utilized a fault-tolerant reversible logic Double Feynman Gate in place of conventional inverters to design the ring oscillators (RO). The proposed RO PUF designs implemented and evaluated on the Basys-3 Artix-7 FPGA board. The PUF parameters such as uniqueness, reliability, and uniformity were analyzed based on the experimental results. The empirical results show that the proposed RO PUF has uniqueness and reliability of 0.49 and 85.95%, respectively. The inter-chip and intra-chip uniqueness for the proposed design is 23% and 25.5%, respectively higher than the conventional RO PUF design. This fault-tolerant reversible logic gate-based RO PUF design shows better uniqueness, reliability, and uniformity than other considered PUF designs.

Asynchronous Reversible Computing Unveiled Using Ballistic Shift Registers

Reversible logic can provide lower switching energy costs relative to all irreversible logic, including those developed by industry in semiconductor circuits, however, more research is needed to understand what is possible. Superconducting logic, an exemplary platform for both irreversible and reversible logic, uses flux quanta to represent bits, and the reversible implementation may switch state with low energy dissipation relative to the energy of a flux quantum. Here we simulate reversible shift register gates that are ballistic: their operation is powered by the input bits alone. A storage loop is added relative to previous gates as a key innovation, which bestows an asynchronous property to the gate such that input bits can arrive at different times as long as their order is clearly preserved. The shift register represents bit states by flux polarity, both in the stored bit as well as the ballistic input and output bits. Its operation consists of the elastic swapping of flux between the stored and the moving bit. This is related to a famous irreversible shift register, developed prior to the advent of superconducting flux quanta logic (which used irreversible gates). In the base design of our ballistic shift register (BSR) there is one 1-input and 1-output port, but we find that we can make other asynchronous ballistic gates by extension. The gate constitutes the first asynchronous reversible 2-input gate. Finally, for a better insight into the dynamics, we introduce a collective coordinate model. We find that the gate can be described as motion in two coordinates subject to a potential determined by the input bit and initial stored flux quantum. Aside from the favorable asynchronous feature, the gate is considered practical in the context of energy efficiency, parameter margins, logical depth, and speed.

Reference Point-based Evolutionary Multi-objective Optimization for Reversible Logic Circuit Synthesis

Reference Point-based Evolutionary Multi-objective Optimization for Reversible Logic Circuit Synthesis

Hybrid Encoding Evolutionary Algorithm for Reversible Logic Synthesis

Variable-length encoding evolutionary algorithm has been proved effective in small and medium-sized reversible logic synthesis. Variable-length chromosome is adopted because the length of optimal reversible circuit is unknown. However, it leads to huge search space. The improved two-stage hybrid encoding synthesis is proposed to reduce the search space and enhance the feasible ratio. Fixed and variable-length encoding are applied in the two stages respectively. Estimated maximum length is obtained through heuristic information from the positive polarity Reed Muller spectra and the fixed chromosome length in the first stage is set to a value less than the maximum one. When the population converges in the first stage and the feasible solution has not found, the second stage starts to work. It employs the original variable-length encoding algorithm, but the optimization problem is simplified through the reduced positive polarity Reed Muller spectra of the best solution from the first stage. Experimental results show that both the fixed-length encoding and the simplified fitness function in the two stages both can decrease the search space and save the synthesis time.

Design of Fault Tolerant Array Multiplier Using Parity Preserving Reversible Gate

The digital designs with Reversible logic are more popular now days because of the increased demand of low power usage. Some of the Reversible logic gates are discussed in this paper. This paper also introduces a Parity Preserving Reversible Gate (PPRG) which is used in the fault tolerant devices design such as adders, subtractors and multipliers. The design of an array multiplier by using fault tolerant parallel adders is discussed in this paper. The fault tolerant parallel adders are designed using fault tolerant full adders and half adders and these adders are designed through Parity Preserving Reversible Gate. These adders and multipliers are useful in designing complex circuits such as ALU.