Reversible Logic Circuits Research Articles

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

New Bounds for Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

Controllable electrical contact characteristics of graphene/Ga2X3 (X = S, Se) ferroelectric heterojunctions

Reducing the interface barrier between metals and semiconductors is crucial for designing high-performance optoelectronic devices based on van der Waals heterojunctions (HJs). This study proposes four models of HJs composed of graphene (GR) and Ga2X3 (X = S, Se) and systematically investigates their interface electronic properties, along with strain engineering and electric field effects. The results indicated that exploiting the interface dipole-induced potential step allows modulation of the Schottky barrier height (SBH) and contact type of the HJs by altering the contact interfaces. In the BGR/Ga2S3 HJs (BGR means GR positioned at the bottom of Ga2X3), only a small positive (negative) electric field is required to realize the transition from n-type Schottky to p-type Schottky (Ohmic) contacts. Also, strain engineering provides additional means for flexible and controllable contact types, facilitating the design of reversible logic circuits. It indicates the physical insights and strategic interventions of GR/Ga2X3 HJs tunable SBH and offers theoretical guidance for the design of two-dimensional ferroelectric nanodevices with high-quality electrical contact interfaces.

Optimized design and investigation of novel reversible toffoli and peres gates using QCA techniques

The QCA is a revolutionary dominating transistor-less computational nanotechnology based on quantum dots. As such, it might be used in the next generation of quantum computational nano-electronics devices. New molecular materials like QCA are being developed for use in nanoscale devices and cables. The major objective of this research is to optimize the design and investigate numerous properties of a QCA reversible logic circuit design. These locations include, limited Toffoli Gate (TG) and Peres Gate (PG). To address the key problems associated with the physical integration of digital circuits is power consumption and power dissipation which leads to synchronization issues, this research proposes a novel reversible logic gates (RLG-TG) a single layer coplanar approach. RLG designs with minimal design area, latency, and quantum cell count (QCA) are given and implemented using a Bijection functional method. Using the QD-E (Energy) tool, the first-order energy dissipation of the proposed shape and the impact of output bias cell temperature are also investigated. The proposed circuit designs were tested using the CVSE parameters, which had high clock signal saturation energies of 9.8e-22 d (Jules), recovery times for damping factors of 1e-15 s, and relative dielectric constants of 12.90 for GaAs and AlGaAs. The number of quantum cells used by the described new RLG-TG and RLG-PG designs is decreased by 38.23 % and 21.14 %, respectively, when compared to the optimal RLG designs employed in the state-of-the-art RLG designs. In this investigation of the proposed four-bit EPG and OPG circuits occupies 18.91 % and 38.27 % less design area, requires 46.15 % and 46.25 % less number of cells, and both designs has been 66.66 % improvement in delay.

The Complexity of Iterated Reversible Computation

We study a class of functional problems reducible to computing $f^{(n)}(x)$ for inputs $n$ and $x$, where $f$ is a polynomial-time bijection. As we prove, the definition is robust against variations in the type of reduction used in its definition, and in whether we require $f$ to have a polynomial-time inverse or to be computible by a reversible logic circuit. These problems are characterized by the complexity class $\mathsf{FP}^{\mathsf{PSPACE}}$, and include natural $\mathsf{FP}^{\mathsf{PSPACE}}$-complete problems in circuit complexity, cellular automata, graph algorithms, and the dynamical systems described by piecewise-linear transformations.

Design‐for‐testability for reversible logic circuits based on bit‐swapping

AbstractThe emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low‐power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k‐CNOT), k ≥ 1. While analysing testability issues in a reversible circuit, the missing‐gate fault model is often used for modelling physical defects in k‐CNOT gates. A new design‐for‐testability (DFT) technique is proposed for reversible circuits that deploys bit‐swapping using Fredkin reversible gates. It is shown that in an (n × n) circuit implemented with k‐CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of maximum size 2n + 1 that detects all detectable missing gate faults in the original circuit, where n is the number of input/output lines in the circuit. The DFT overhead in terms of quantum cost is much less compared to that of previous approaches. The method is more advantageous for large circuits.

Reference Point-based Evolutionary Multi-objective Optimization for Reversible Logic Circuit Synthesis

Reference Point-based Evolutionary Multi-objective Optimization for Reversible Logic Circuit Synthesis

A new design for XOR gate-based reversible double Feynman gate in nano-scale quantum-dots

Quantum-dot Cellular Automata (QCA), which provides a novel technique for fabricating energy-efficient nano-scale digital circuits, can replace transistor-based technologies. But, in this technology, designing a reliable and reversible circuit design is very important. The use of reversible logic gates in QCA has piqued the interest of a wide range of researchers. However, designing QCA-based architecture for reversible logic circuits still has ample space. The previous circuits in this field have some disadvantages, such as the lack of easy access to inputs and outputs, low speed, and a high number of consumed cells, which have caused the lack of expandability of circuits. Therefore, there is a need to design smaller and faster circuits with easier access to inputs and outputs so that in addition to achieving high speed, reversibility can be extended to other circuits as well. As a result, this study presents a helpful topology for implementing a reversible circuit based on the innovative XOR gate. In this design, a reversible circuit is designed using 2 two-input XOR gates, cell arrangement, and columbic repulsion. It can be integrated with other gates to test the performance of the circuit, its reversibility, and its expansion. To test the extendability of the proposed circuit, we also considered a 4-bit binary to gray code converter. The suggested ideas are tested by running simulations using the QCADesigner-E. The suggested construction consists of 19 cells and takes up only 0.03 µm2. The results confirmed that the design has stable and applicable size, cost, and structures. The proposed architecture is also simple to use on bigger circuits and offers easy access to input and output.

Design and Implementation of Seven Segment Display Using Reversible Logic Gates

Abstract: An important issue in Seven segment display is heat, but the reversible logic gives less amount of heat dissipation. So, it’s an important role in nanotechnology, less energy complementary metal oxide semiconductor CMOS designs etc. Seven segment displays are most effective devices used in electronic meters, digital calculators, clock radios, digital clocks, odometers, displays in home appliances, etc.In this project, an efficient seven segment display is designed using reversible logic gates CNOT, FREDKIN and PERES gates. Retrievability is a feature which every electronic device wants to posses , In reversible logic gates the inputs and outputs can be retrievable from each other. Backward operation is used in this circuit which allows to retrieve the inputs from the outputs therefore consuming zero power. Reversible logic circuits are also known as lossless circuits, which has neither information loss nor energy loss. The reversible logic operations dissipate less heat and can't erase information.

Design and Analysis of Novel Non-Reversible & Reversible Parity Generator and Detector in Quantum Cellular Automata using Feynman Gate

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Conclusion: Using reversible logic, a fault-tolerant and defect-sensitive circuit are developed for parity generation and detection.

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an [Formula: see text] reversible circuit implemented with [Formula: see text]-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size [Formula: see text] to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

Silicon microring resonator based on all-optical reversible modified Fredkin gate: design and analysis

The conventional logic circuits dissipate energy into the environment due to the loss of information; hence these are termed irreversible logic circuits. The reversible logic (RL) circuits are capable of minimizing the power dissemination, quantum cost, and garbage outputs. The RL circuits based on all-optical technology have been adopted by many researchers in recent. The Fredkin gate is a significant RL gate. A modified Fredkin gate (MFG) made of a silicon all-optical microring resonator is realized in MATLAB. The MFG is capable of designing 16-Boolean functions with very small complexity. The figure of merit of the proposed MFG is achieved through numerical simulation. The parameters are selected from the determined specifications, and this could provide a practicable implementation of the proposed design.

Energy-aware estimation and management models for quantum dot cellular automata

Nowadays, the Quantum-dot Cellular Automata (QCA) cells as emerging digital systems are applied to designing digital complex circuits, subtractors, full adder, and flip flop structures. Also, many research studies have paid attention to optimizing and minimizing energy management and power consumption using reversible and single-layer logic circuits methods. The energy estimation and power calculation of QCA cells are emerging research issues in digital design circuits. To overcome optimizing energy management and power consumption of QCA cells, a comparison of existing methodologies can be useful to get the best outcomes and research direction. This paper provides a comprehensive and technical analysis of the existing optimized energy-aware estimation and management methodologies for QCA. Also, some important technical evaluation factors, tools, and designs are discussed and compared. Finally, new open issues and current challenges are shown with a point-to-point technical strategy.

Hydrazone-based Schiff base dual chemosensor for recognition of Cu2+ and F− by 1:2 demultiplexer, half adder, half subtractor, molecular keypad lock and logically reversible transfer gate logic circuits and its application as test kit

A new hydrazone-based chemosensor R was synthesized as a highly colorimetric and fluorescent sensor for Cu2+ and F− ions in DMSO. The chemosensor R characterized by UV–Vis absorption and fluorescence spectroscopic studies. The binding behavior of the chemosensor R toward Cu2+ and F− ions was investigated by UV–Vis absorption, 1HNMR and fluorescence spectroscopic studies. By adding Cu2+ ion to the chemosensor R, a mental-to-ligand charge-transfer transition (MLCT) was exhibited at 410 nm and the decrease of fluorescence at 532 nm was observed with concomitant appearance of a new peak at 570 nm. A new absorption peak at 513 nm and enhancement of the emission band at 532 nm were observed in the presence of F− ions. The –NH unit in hydrazone- based chemoreceptor is the proper H-bond donor which can act as a selective sensor for F− ions. The detection limits of the compound R (obtained by the 3σ method) for Cu2+ and F− ions are 3.51 × 10−6 and 3.26 × 10−6 mol L−1, respectively. According to the observed changes in the absorbance and emission intensity a specific wavelength as a result of two inputs (Cu2+ and F−), it can be concluded that the chemosensor R mimics the function of XOR, INH, IMP and AND logic gates and half adder, half subtractor, 1:2 demultiplexer, complementary IMP/INH logic, molecular keypad lock and logically reversible transfer gate logic circuits with a single molecule. The test kits can be utilized for detecting fluoride anion with different concentration in aqueous media by naked-eyes, without any optical instrument in undeveloped regions.

RETRACTED: High speed low power multipliers based on reversible logic methods

The aim of this research is on multipliers with higher speed, less power consumption, and a lower-complexity lower range. Reversible logic has recently found extensive application in multiple areas including multipliers, low-power CMOS circuits, optical data processing, and quantum circuits. Here, reversible logic is used to create efficient multipliers that are constructed with Vedic mathematics, Baugh-Wooley, and Wallace tree architectures. A particularly nice thing about these proposed multipliers is that they all utilize known logical principles, such as the reversible Half Adder, the reversible Full Adder, the Dual Key Gate, and the Kogge Stone Adder. As a means of guaranteeing better performance, multiple multipliers are distinguished according to reversible logic circuits. Simulated and synthesized using the Xilinx ISE method, the results of the proposed design are investigated.

Design And Implementation Of 64-Bit Ripple Carry Adder And Ripple Borrow Subtractor Using Reversible Logic Gates

Minimal power design is desirable for a range of applications, including the Internet of Things (IoT), quantum computing, and so on. The reversible logic approach is at the foundation of a new technique for designing minimal power digital logic circuits for quantum computing applications. The reversible logic circuit offers a whole new approach to quantum computer processing. Reversible logic gates-based devices will be in high demand for future computer technologies since they require less power. Reversible logic gates were used to design a ripple carry adder (RCA) and a ripple borrow subtractor (RBS), which were simulated in Verilog 2018.3 and coded in Verilog HDL.

Reversible Gate Logic Adder with Parity Preserving Design

Reversible logic circuits have drawn attention from a variety of fields, including nanotechnology, optical computing, quantum computing, and low-power CMOS design. Low-power and high-speed adder cells (like the BCD adder) are used in binary operation-based electronics. The most fundamental digital circuit activity is binary addition. It serves as a foundation for all subsequent mathematical operations. The main challenge today is to reduce the power consumption of adder circuits while maintaining excellent performance over a wide range of circuit layouts. Error detection in digital systems is aided by parity preservation. This article proposes a concept for a fault-tolerant parity- preserving BCD adder. To reduce power consumption and circuit quantum cost, the proposed method makes use of reversible logic gates like IG, FRG, and F2G. Comparing the proposed circuit to the current counterpart, it has fewer constant inputs and garbage outputting devices and is faster.

An all-optical equalizer SWAP gate (ESG)

A reversible logic gate differs from the conversational logic gate in many ways, such as equal number of input–output, its reverse operation and bijective input/output mapping. In this paper, a new class of 4 4 conservative-reversible logic gate named the equalizer SWAP gate (ESG) has been proposed. This gate is self-invertible and performs SWAP operation when two of its control inputs are logic either 0 or 1. The all-optical design of the ESG using a ‘semiconductor optical amplifier (SOA) assisted Sagnac interferometer’ with a counter-propagating signal passing through the SOA has been shown with a mathematical model in this paper. Quantum realization of the ESG has been carried out to construct its unitary matrix. Also, the matrix has been established through numerical simulation. Some complex reversible logic circuits, viz. n-bit XOR/XNOR, full-adder circuit, n-bit binary-to-gray and gray-to-binary conversion, using the ESG unit have also been shown. Simulated outputs, logical complexity, quantum realization, optical cost and delay of the proposed circuit have been analyzed, and are compared with other reversible logic gates.

Design and implementation of reversible logic gates using silicene-based p–n junction logic devices

Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively.

Synthesis of Reversible and Quantum Circuit Using ROCBDD and Mixed-Polarity Toffoli Gate

In the last decade, the synthesis of reversible logic circuits has become a trending topic because of its future necessity and importance. Many methods have been studied and proposed, for instance, transformation-based, search-based, cycle-based, ESOP-based and BDD-based methods. Each of them has its limitation related to time processing, ancilla and garbage line, quantum cost. This study develops an algorithm that could synthesize quantum circuits based on mixed-polarity Toffoli gate and a variant of binary decision diagram (BDD) called reduced-ordered-complemented edge-bdd (ROCBDD). It is an optimized method of BDD to reduce nodes in the representation of Boolean functions, which leads to adding more lines and quantum gates in the reversible circuit. First, the differences between synthesis using ROCBDD, the traditional BDD and others methods are introduced. Then, we define a new structure consisting of mixed-polarity Toffoli gates relied on nodes of ROCBDD. An efficient algorithm to match BDD representation to the reversible logic circuit is also mentioned. Finally, the experimental results show that our algorithm has better synthesizing costs than previous BDD-based methods.

Quantum image filtering and its reversible logic circuit design

Quantum information processing can overcome the limitations of classical computation. Consequently, image filtering using quantum computation has become a research hotspot. Here, a quantum algorithm is presented on the basis of the classical image filtering principle to detect and cancel the noise of an image. To this end, a quantum algorithm that completes the image filtering task is proposed and implemented. The novel enhanced quantum representation of digital images is introduced. Then, four basic modules, namely, position-shifting, parallel-CNOT, parallel-swap, and compare the max, are demonstrated. Two composite modules that can be utilised to realise the reversible logic circuit of the proposed quantum algorithm are designed on the basis of these basic modules. Simulation-based experimental results show the feasibility and the capabilities of the proposed quantum image filtering scheme. In addition, our proposal has outperformed its classical counterpart and other existing quantum image filtering schemes supported by detailed theoretical analysis of the computational complexity. Thus, it can potentially be used for highly efficient image filtering in a quantum computer age.