Reversible Logic Circuits Research Articles

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

Low Cost Reversible Signed Comparator

Nowadays exponential advancement in reversible computation has lead to better fabrication and integration process. It has become very popular over the last few years since reversible logic circuits dramatically reduce energy loss. It consumes less power by recovering bit loss from its unique input-output mapping. This paper presents two new gates called RC-I and RC-II to design an n-bit signed binary comparator where simulation results show that the proposed circuit works correctly and gives significantly better performance than the existing counterparts. An algorithm has been presented in this paper for constructing an optimized reversible n-bit signed comparator circuit. Moreover some lower bounds have been proposed on the quantum cost, the numbers of gates used and the number of garbage outputs generated for designing a low cost reversible signed comparator. The comparative study shows that the proposed design exhibits superior performance considering all the efficiency parameters of reversible logic design which includes number of gates used, quantum cost, garbage output and constant inputs. This proposed design has certainly outperformed all the other existing approaches.

Reversible Arithmetic Logic Gate (ALG) for Quantum Computation

At present, Boolean algebra based computations by the use of silicon based semiconductor technology are irreversible in nature. This is due to the mismatch of number of inputs and outputs. Reversible logic circuit maps unique input to the output and ensure one to one mapping and basis for emerging applications like low-power design, quantum computation, optical computing, bioinformatics and nanotechnologies. In computing paradigm, Arithmetic Logic Unit (ALU) is one of the computing intensive building blocks of the computer that performs arithmetic and logical operations. This work understands and nurtures the necessity of reversible ALU for future revolutionary computing technologies. In this paper, a 4x4 reversible gate which alone performs arithmetic and logic operations is proposed and compared with other reversible gates like TSG, HNG and MKG, in terms of quantum cost, I/O lines and Taffoli gates. The results of different synthesis methods of 4x4 ALG using Revkit tool are studied. Proposed gate performs better than existing methods and ensures maximum logical operations like full adder, full subtractor and all logical operations with less hardware cost where other existing gates are not viable.

Novel designs for fault tolerant reversible binary coded decimal adders

Reversible logic circuits have received emerging attentions in recent years. Reversible logic is widely applied in some new technical fields, such as quantum computing, nanocomputing and optical computing and so on. In this paper, three fault tolerant gates are proposed, ZPL gate, ZQC gate and ZC gate. By using the proposed gates, fault tolerant quantum and reversible BCD adder and skip carry BCD adder are designed, which overcome the limitations of the existing methods. The proposed reversible BCD adders have also parity-preserving property. They are better than the existing counterparts, especially in the quantum cost. Proposed designs have been compared with existing designs with respect to the number of gates, number of garbage outputs and quantum cost.

Online Testable Approaches in Reversible Logic

We present an overview and analysis of existing work in the design of online testable reversible logic circuits, as well as propose new approaches for the design of such circuits. We explain how previously proposed approaches are unnecessarily high in overhead and in many cases do not provide adequate fault coverage. Proofs of the correctness of our approaches are provided, and discussions of the advantages and disadvantages of each design approach are given. Experimental results comparing our approaches to existing work are presented as well. Both approaches that we propose have better fault coverage and significantly lower overheads than previous approaches.

A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

Reversible logic is becoming one of the best emerging design approaches for future computation of reversible logic having its more application in low power application. This logic is applied in the quantum computers, optical computing, communication and nanotechnology. In reversible logic approach generates the garbage input/output. In this paper design of proposed reversible logic multiplexer with garbage input/output, that the low power, area design technique are using that is the Gate -Diffusion -Input (GDI cell) in this dynamic component of power is reduced, In GDI cell PMOS is not connected to supply voltage VDD and NMOS is not connected to the GND.GDI circuits provide some measure issues of enhanced hazard tolerance and low voltage operation of reversible logic circuits. In this paper propose a novel application of GDI (Gate-Diffusion Input) circuits to Reversible logic multiplexer with its Garbage input and output. The new proposed design technique will consume less power than the other traditional gate. In recent years ago reversible logic circuit is less power dissipation. This GDI cell technique reduces the power of the circuit, delay, PowerDelay Product (PDP) and it also reduced frequency. The device scaling is limited by the power dissipation are more optimize in terms of delay, power supply, frequency , duty cycle, frequency jitter bandwidth of the signal and also demonstrated the noise of the circuit. The proposed reversible logic design. the GDI is effective in low power, low leakage current and lower Delay, The transistor implementation of the proposed gates is done by using Virtuoso tool of cadence. Based on simulation results and analysis at 45 nm technology, some of the trade-offs are made in the design to improve the efficiency.

Synthesis and optimization of reversible circuits—a survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, postsynthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms—search based, cycle based, transformation based, and BDD based—as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.

4 Bit Comparator Design Based on Reversible Logic Gates

Today, reversible logic circuits has attracted considerable attention in improving some fields like nanotechnology, quantum computing, and low power design. In this paper 4 bit reversible comparator based on classical logic circuit is represented which uses existing reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The results show that, the proposed comparator has 4 quantum cost and one constant input less than the prior design. 1

Efficient Algorithms for Optimal 4-Bit Reversible Logic System Synthesis

Owing to the exponential nature of the memory and run-time complexity, many methods can only synthesize 3-bit reversible circuits and cannot synthesize 4-bit reversible circuits well. We mainly absorb the ideas of our 3-bit synthesis algorithms based on hash table and present the efficient algorithms which can construct almost all optimal 4-bit reversible logic circuits with many types of gates and at mini-length cost based on constructing the shortest coding and the specific topological compression; thus, the lossless compression ratio of the space ofn-bit circuits reaches near2×n!. This paper presents the first work to create all 3120218828 optimal 4-bit reversible circuits with up to 8 gates for the CNT (Controlled-NOT gate, NOT gate, and Toffoli gate) library, and it can quickly achieve 16 steps through specific cascading created circuits.

Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.

Design of 1-tape 2-symbol reversible Turing machines based on reversible logic elements

This paper proposes a novel scheme for constructing reversible Turing machines (RTMs) via various reversible logic elements. A reversible logic element is similar to a conventional reversible logic gate, except that the element also carries a 1-bit memory that can store binary states. The usage of internal states allows much more efficient and straightforward constructions of RTMs based on reversible elements than based on reversible logic gates. In particular, a remarkable feature of our constructions is that they can operate asynchronously, whereby the clock signal, which is indispensable for synchronizing all elements as in a reversible logic circuit, can possibly be removed from the construction.

DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS

The majority of work in reversible logic circuits has been limited to combinational logic. Researchers are now beginning to suggest designs for sequential circuits. In this paper we propose a new method to design and optimize feedback reversible logic circuits and a specific group of quantum logic circuits based on the reversible state transition table and genetic algorithms (GA). To show the efficiency of the proposed method, some reversible sequential elements such as D and T flip-flops (FFs), with and without clock and reset, and edge triggered FFs are designed. We have also extended our method to multiple loop feedback circuits. The proposed circuits are highly optimized using a GA synthesis tool that allows don't care values. Some of the designs in this paper are presented in other papers; however, the comparisons show that the quantum cost and number of garbage inputs/outputs are reduced efficiently by our method.

Design of fast fault tolerant reversible signed multiplier

Reversible logic circuits are emerging as a promising technology for power minimization. Parity preserving reversible circuits design will be very important for development of fault tolerant reversible systems in nanotechnology. In this paper, a fast fault tolerant reversible signed multiplier is proposed. In order to construct the multiplier, five variables parity preserving gate (F2PG) and modified new fault tolerant (MNFT) are designed, which are parity preserving reversible gates. The most significant aspect of F2PG is that it can work independently as a reversible fault tolerant full adder. Meanwhile, it can implement all Boolean functions. MNFT can reduce cross redundancy. The quantum implementations of F2PG and MNFT are also given. Otherwise, a new quantum implementation of the modified Islam gate (MIG) is presented. The Wallace tree is applied to improve the operating speed of the multiplier, which can implement the multiplication of two 5-bit binary signed numbers. Simulation and evaluation results indicate that the multiplier logic structure is correct with excellent performance. Key words: Parity preserving reversible gate, fault tolerant, five variables parity preserving gate (F2PG), modified new fault tolerant (MNFT), reversible signed multiplier.

Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares

In this paper, a synthesis method for combinational multiple-valued reversible logic (MVRL) circuits is proposed. This algorithm can use the don't care values in the synthesis process to obtain the optimal circuit with respect to quantum cost. The binary Fredkin gate is extended to the MVRL Fredkin gate, and its synthesis using 2×2 gates is proposed. Additionally, we have used the algorithm to design sequential MVRL circuits based on the state transition table. We propose three generalized designs for T, D, and JK flip flops (FF). The generalized r-valued T-FF is designed using 2r−3 controlled Cycle gates (r stands for radix). The r-valued D-FF is designed using the new version of the MVRL Fredkin gate. The ternary JK-FF, which performs nine distinct functions, is designed using only seven controlled Cycle gates. These FFs are the essential circuits to design MVRL state machines, and we synthesize the circuits with the minimal number of constant inputs and garbage outputs.

Reversible Logic Circuits Made of DNA

We report reversible logic circuits made of DNA. The circuits are based on an AND gate that is designed to be thermodynamically and kinetically reversible and to respond nonlinearly to the concentrations of its input molecules. The circuits continuously recompute their outputs, allowing them to respond to changing inputs. They are robust to imperfections in their inputs.

A novel nanometric fault tolerant reversible divider

Quantum and reversible logic circuits have more advantages than the common circuits, like low power consumption. These circuits are good choice to design future computers. One of the important issues in reversible logic is parity preservation. If parity of inputs and outputs are equal in reversible gate, this gate will be parity preserve. Reversible circuits made by these gates are parity preserve. In this paper we propose a new fault tolerant reversible divider. The proposed fault tolerant reversible divider is the first effort to design fault tolerant reversible division circuit. In this circuit, we use some fault tolerant reversible components like fault tolerant reversible parallel adder, fault tolerant reversible shift register and fault tolerant reversible n-bit register. Hence, we also propose a new fault tolerant reversible full adder, a new fault tolerant reversible n+1-bit parallel adder and a new basic cell for PIPO fault tolerant reversible left-shift register. These parity preserving reversible components are also proposed for the first time in the literature. All the scales are in the nanometric area. Key words: Reversible logic, parity preservation, fault tolerant, nanometric circuits, reversible divider.

A NOVEL REVERSIBLE ZS GATE AND ITS APPLICATION FOR OPTIMIZATION OF QUANTUM ADDER CIRCUITS

The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles

One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non-adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for 2LAL, and 17% for SCRL) the energy dissipation arising from the breaking reversibility problem.

NOVEL QUANTUM COMPRESSOR DESIGNS USING NEW GENETIC ALGORITHM-BASED SIMULATOR, ANALYZER AND SYNTHESIZER SOFTWARE IN NANOTECHNOLOGY

Quantum and reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing, and low power CMOS design. In this paper, we propose some new quantum and reversible compressors using our new genetic algorithm-based simulator, analyzer, and synthesizer software. The proposed quantum 4:2 and 6:2 compressor circuits are compared with the existing counterparts in terms of number of constant inputs, number of garbage outputs, delay and the quantum cost (QC). We have also designed quantum 7:2 compressor for the first time. The proposed quantum compressors are optimized in terms of QC and delay. The proposed designs can be used as a basic block in complex systems like multipliers, and can execute complicated operations better than the existing designs in literature.