Reversible Logic Circuits Research Articles

Estimation of Power for Reversible Subtractors

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG). Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor. Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.

An efficient quantum compiler that reduces T count

Before executing a quantum algorithm, one must first decompose the algorithm into machine-level instructions compatible with the architecture of the quantum computer, a process known as quantum compiling. There are many different quantum circuit decompositions for the same algorithm but it is desirable to compile leaner circuits. A fundamentally important cost metric is the T count—the number of T gates in a circuit. For the single qubit case, optimal compiling is essentially a solved problem. However, multi-qubit compiling is a harder problem with optimal algorithms requiring classical runtime exponential in the number of qubits. Here, we present and compare several efficient quantum compilers for multi-qubit Clifford + T circuits. We implemented our compilers in C++ and benchmarked them on random circuits, from which we determine that our TODD compiler yields the lowest T counts on average. We also benchmarked TODD on a library of reversible logic circuits that appear in quantum algorithms and found that it reduced the T count for 97% of the circuits with an average T-count saving of 20% when compared against the best of all previous circuit decompositions.

Testable Design of Reversible Circuits Using Parity Preserving Gates

This paper proposes an efficient design for testability technique for reversible logic circuits, which promises ultralow energy computation.

Designing and Implementation of Efficient (2i x j) Reversible RAM-Array Module

In the modern digital-world, power dissipation in microprocessors is becoming a significant challenge for the researchers to design an efficient reversible logic circuit. Thus, study on reversible logic design has been rapidly increased in present days for its application in Nano technology as well as in low energized VLSI design etc. In this current study, have realized a QC (i.e. quantum-cost) efficient (2i x j) reversible RAM array module with (3 x 3) New Modified Fredkin (NMF) reversible gate. Additionally, have introduced a Reversible D-Flip-Flop (RDFF) with less QC, and Reversible (i x 2i) decoder which produces the effective results in terms of QC and garbage-outputs. Finally, the study analyzed the designed architecture in terms of worst case delay.

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

An efficient design for reversible Wallace unsigned multiplier

Today, reversible logic can be used for designing low-power CMOS circuits, optical data processing, DNA computations, biological researches, quantum circuits and nanotechnology. Sometimes using of reversible logic is inevitable such as build quantum computers. Reversible logic circuits structure is much more complicated than irreversible logic circuits. Multiplication operation is considered as one of the most important operations in the ALU unit. In this paper, we have proposed two 4 × 4 reversible unsigned multiplier circuits in which Wallace tree method is used to reduce the depth of circuits. In first design, the partial products circuit is designed using TG and FG gates so that TG is used to produce the partial products and FG for fan-out. In the second design, TG and PG gates are used to produce the partial products and no fan-out is required. Moreover, we have used PG gate and Feynman' block as reversible half-adder (HA) and full-adder (FA) in the summation network, respectively. In the first design, the main purpose is to decrease the depth of the circuit and increase the circuit speed. In the second design we would attempt to improve quantum parameters the number of garbage outputs, constant inputs and quantum cost. The evaluation results show that the first design, in terms of delay, is the fastest circuit. Also, the second design in terms of the number of constant inputs, garbage outputs and quantum cost is better than other designs.

Reversible magnetic logic gates based on spin wave interference

We propose and develop reversible magnetic logic gates based on spin wave interference. The gates consist of passive elements including spin waveguides, cross-junctions, and phase shifters. Logic 0 and 1 are encoded in the phase of the propagating spin wave (0 or π). There are different possible input-output trajectories for the propagating spin waves, where some of the trajectories contain phase shifters and others do not. In each case, the particular input-output trajectory and the resultant output phase depend on the input phase combination. The redirection takes place in the cross junctions. Two waves coming to a junction in-phase propagate through the junction without reflection. In contrast, two waves coming to a junction out-of-phase are completely reflected back. The process of redirection is illustrated by numerical modeling of a nanometer-scale junction comprising two chains of spins, which operates at zero temperature. We also present experimental data on spin wave redirection in a micrometer-size cross junction made of Y3Fe2(FeO4)3 operating at room temperature. Our results demonstrate a prominent spin wave redirection, where the ratio of the transmitted power between the in-phase and out-of-phase cases exceeds 45 dB at room temperature. Based on these experimental data, we estimate the energy per operation in spin wave reversible logic circuits. The proposed reversible gates may provide a route to magnetic logic circuitry with power dissipation less than kT per operation.

Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks

The quantum of power consumption in wireless sensor nodes plays a vital role in power management since more number of functional elements are integrated in a smaller space and operated at very high frequencies. In addition, the variations in the power consumption pave the way for power analysis attacks in which the attacker gains control of the secret parameters involved in the cryptographic implementation embedded in the wireless sensor nodes. Hence, a strong countermeasure is required to provide adequate security in these systems. Traditional digital logic gates are used to build the circuits in wireless sensor nodes and the primary reason for its power consumption is the absence of reversibility property in those gates. These irreversible logic gates consume power as heat due to the loss of per bit information. In order to minimize the power consumption and in turn to circumvent the issues related to power analysis attacks, reversible logic gates can be used in wireless sensor nodes. This shifts the focus from power-hungry irreversible gates to potentially powerful circuits based on controllable quantum systems. Reversible logic gates theoretically consume zero power and have accurate quantum circuit model for practical realization such as quantum computers and implementations based on quantum dot cellular automata. One of the key components in wireless sensor nodes is the cryptographic algorithm implementation which is used to secure the information collected by the sensor nodes. In this work, a novel reversible gate design of 128-bit Advanced Encryption Standard (AES) cryptographic algorithm is presented. The complete structure of AES algorithm is designed by using combinational logic circuits and further they are mapped to reversible logic circuits. The proposed architectures make use of Toffoli family of reversible gates. The performance metrics such as gate count and quantum cost of the proposed designs are rigorously analyzed with respect to the existing designs and are properly tabulated. Our proposed reversible design of AES algorithm shows considerable improvements in the performance metrics when compared to existing designs.

Design and Implementation of a Reversible Logic Circuit and Its Power Analysis Using Conventional CMOS and Adiabatic Logic

Design and Implementation of a Reversible Logic Circuit and Its Power Analysis Using Conventional CMOS and Adiabatic Logic

Алгоритм минимизации функций алгебры логики в классе обратимых схем Тоффоли

Алгоритм минимизации функций алгебры логики в классе обратимых схем Тоффоли

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic...

Experimental demonstration of an optical Feynman gate for reversible logic operation using silicon micro-ring resonators

Abstract Currently, the reversible logic circuit is a popular research topic in the field of information processing as it is a most effective approach to minimize power consumption, which can achieve the one-to-one mapping function to identify the input signals from its corresponding output signals. In this letter, we propose and experimentally demonstrate an optical Feynman gate for reversible logic operation using silicon micro-ring resonators (MRRs). Two electrical input signals (logic operands) are applied across the micro-heaters above MRRs to determine the switching states of MRRs, and the reversible logic operation results are directed to the output ports in the form of light, respectively. For proof of concept, the thermo-optic modulation scheme is used to achieve MRR’s optical switching function. At last, a Feynman gate for reversible logic operation with the speed of 10 kbps is demonstrated successfully.

Reversible binary subtractor design using quantum dot-cellular automata

In the field of nanotechnology, quantum dot-cellular automata (QCA) is the promising archetype that can provide an alternative solution to conventional complementary metal oxide semiconductor (CMOS) circuit. QCA has high device density, high operating speed, and extremely low power consumption. Reversible logic has widespread applications in QCA. Researchers have explored several designs of QCA-based reversible logic circuits, but still not much work has been reported on QCA-based reversible binary subtractors. The low power dissipation and high circuit density of QCA pledge the energy-efficient design of logic circuit at a nano-scale level. However, the necessity of too many logic gates and detrimental garbage outputs may limit the functionality of a QCA-based logic circuit. In this paper we describe the design and implementation of a DG gate in QCA. The universal nature of the DG gate has been established. The QCA building block of the DG gate is used to achieve new reversible binary subtractors. The proposed reversible subtractors have low quantum cost and garbage outputs compared to the existing reversible subtractors. The proposed circuits are designed and simulated using QCA Designer-2.0.3.

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.

Reversible circuit synthesis by genetic programming using dynamic gate libraries

We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

Floating point digital signal processing technology has become the primary method for real time signal processing in most digital systems presently. However, the challenges in the implementation of floating point arithmetic on FPGA are that, the hardware modules are larger, have longer latency and high power consumption. In this work, a novel efficient reversible floating point fused arithmetic unit architecture is proposed confirming to IEEE 754 standard. By utilizing reversible logic circuits and implementation with adiabatic logic, power efficiency is achieved. The hardware complexity is reduced by employing fused elements and latency is improved by decomposing the operands in the realization of floating point multiplier and square root. To validate the design, the proposed unit was used for realization of FFT and FIR filter which are important applications of a DSP processor. As detection is one of the core baseband processing operations in digital communication receivers and the detection speed determines the data rates that can be achieved, the proposed unit has been used to implement the detection function. Simulation results and comparative studies with existing works demonstrate that the proposed unit efficiently utilizes the number of gates, has reduced quantum cost and produced less garbage outputs with low latency, thereby making the design a computational and power efficient one.

On asymptotic gate complexity and depth of reversible circuits without additional memory

In the paper we study reversible logic circuits, which consist of NOT, CNOT and C2NOT gates. We consider a set F(n,q) of all transformations Bn→Bn that can be realized by reversible circuits with (n+q) inputs. We define the Shannon gate complexity function L(n,q) and the depth function D(n,q) as functions of n and the number of additional inputs q. We prove general lower bounds for these functions. We introduce a new group-theory-based synthesis algorithm that can produce a reversible circuit S without additional inputs and with the gate complexity L(S)≤3n2n+4(1+o(1))/log2⁡n in the worst case.

Design & Performance Analysis of Low Power Reversible Residue Adder

Reversible logic is a concept of digital circuit design which was invented with the concept of creating digital logic circuits with zero power consumption and minimum power loss. It replaces irreversible logic gates with reversible gates in the conventional digital circuits. Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation .Normal combinational logic circuits dissipate heat for every bit of information lost during their operation. Due to this the recovery of a piece of information once lost is completely impossible. However, if the same circuit is constructed using the reversible logic gates, not only is the recovery possible but also the dissipation of heat reduced. According to Rolf Landauer (1961), whenever we use a logically irreversible gate we dissipate energy into the environment. The loss of information is associated with laws of physics requiring that one bit of information lost dissipates kTln2 of energy, where k is Boltzmann’ constant and T is the temperature of the system. Interest in reversible computation arises from the desire to reduce heat dissipation, thereby allowing [1]: I. Higher densities II. Higher speed Later Bennett, in 1973, showed that this KTln2 joules of energy dissipation in a circuit can be avoided if it is constructed using reversible logic circuits [2]. According to Moore’s law, the number of chip components doubling every 18 months, the irreversible technologies would dissipate a lot of heat and heat reduces circuit life. Reversible logic not only recovers the lost information but also dissipate less heat. A Reversible Logic Gate is an n-input, n-output device with One-to-One Mapping, which helps in determining the outputs from the inputs and vice versa. An important On lin e V ers ion O nly .

Novel low-cost and fault-tolerant reversible logic adders

In recent years, reversible logic circuits have received considerable attention due to their diverse applications in various fields. As the computing systems are susceptible to different environmental effects which can impact their intended operations, having the fault-tolerance capability is of great importance. In this paper, at first, a novel reversible gate is presented to achieve a parity preserving full adder which serves as the main building block of different adders. Further on, by using the proposed full adder and new arrangements of other reversible gates, some new low-cost fault-tolerant adders including binary coded decimal, carry skip and carry look-ahead architectures are presented. The new adders are highly efficient in the quantum cost, total logical calculation and transistor count compared to the existing designs. In addition, regarding other factors including the number of gates, garbage outputs and maximum delay, they are the best or among the favorite parity preserving reversible adders.

Design of reversible circuits with high testability

A new method of designing reversible logic circuits which can be adopted by any synthesis technique to produce parity preserving reversible circuits based on Multiple Controlled Tofolli gates is proposed. The designed circuit using proposed methodology is easily testable by checking the input and output parity. A set of benchmark circuits and corresponding testable designs are implemented. The results under testable designs show an average reduction of 32% in operating cost as compared to prior work.