RETRACTED: High speed low power multipliers based on reversible logic methods

Abstract

The aim of this research is on multipliers with higher speed, less power consumption, and a lower-complexity lower range. Reversible logic has recently found extensive application in multiple areas including multipliers, low-power CMOS circuits, optical data processing, and quantum circuits. Here, reversible logic is used to create efficient multipliers that are constructed with Vedic mathematics, Baugh-Wooley, and Wallace tree architectures. A particularly nice thing about these proposed multipliers is that they all utilize known logical principles, such as the reversible Half Adder, the reversible Full Adder, the Dual Key Gate, and the Kogge Stone Adder. As a means of guaranteeing better performance, multiple multipliers are distinguished according to reversible logic circuits. Simulated and synthesized using the Xilinx ISE method, the results of the proposed design are investigated.