Reverse Current Research Articles

Адаптация системы ЧПУ станка к условиям комбинированной обработки

Introduction. Increasing the efficiency of processing technologies for products made from modern high-strength, difficult-to-process materials with increased physical, mechanical and operational properties consists not only in improving the technology itself, the tools for its implementation, but also in modernizing technological equipment taking into account new achievements in the field of mechanical engineering. Modern computer numerical control (CNC) equipment is now quite advanced in terms of controlling basic cutting movements. Adaptive monitoring and control systems, as a rule, additionally installed on processing equipment, make it possible to further improve the quality of processing parameters. With the development of new hybrid and combined technologies that combine several types of influence on the product being processed, the issue of synchronizing the automatic control of the movements of parts of technological equipment with the control and management of accompanying processes of combined technologies has become acute. One example of such technologies is electrochemical diamond grinding with periodic dressing of the working surface of a diamond wheel using reverse polarity current. The polarity of the current and the duration of its pulses are controlled by special programmable devices. Current switching units are connected to it. It serves to supply alternating currents of direct and reverse polarity to the electrical circuit and is made on the basis of key elements. Installing such programmable devices on CNC machines leads to its’ equipping with an additional autonomous automatic control system. At the same time, it is difficult to coordinate the operation of the machine’s CNC system, which controls the movements of its working parts, and the programmable device used to control the polarity and duration of current pulses during combined processing. The purpose of the work is to synchronize the CNC system of the machine with the control system for the process of periodically changing the polarity of the current. The study was carried out on an experimental stand. Methods. The research methodology involved conducting an experiment consisting of synchronizing the operation of the machine’s CNC system with the operation of the control system for the process of periodically changing the polarity of the current. To evaluate the results, the time of movement of the diamond wheel as a result of the working stroke was compared with the duration of current pulses of different polarities specified in the control program of the developed software. Results and discussions. As a result of the research, it is established that the developed software and hardware complex makes it possible to synchronize in the CNC system of the machine tool the control of the movements of the working parts with automatic control of the periodic change of current polarity during electrochemical diamond grinding, which can significantly expand the technical capabilities of CNC machines.

Current transport mechanism of lateral Schottky barrier diodes on β-Ga2O3/SiC structure with atomic level interface

Heterogeneous integration of β-Ga2O3 on highly thermal conductive SiC substrate by the ion-cutting technique is an effective solution to break the heat-dissipation bottleneck of β-Ga2O3 power electronics. In order to acquire high-quality β-Ga2O3 materials on SiC substrates, it is essential to understand the influence of the ion-cutting process on the current transport in β-Ga2O3 devices and to further optimize the electrical characteristics of the exfoliated β-Ga2O3 materials. In this work, the high quality of β-Ga2O3/SiC structure was constructed by the ion-cutting process, in which an amorphous layer of only 1.2 nm was formed between β-Ga2O3 and SiC. The current transport characteristics of Au/Pt/Ni/β-Ga2O3 Schottky barrier diodes (SBDs) on SiC were systematically investigated. β-Ga2O3 SBDs with a high rectification ratio of 108 were realized on a heterogeneous β-Ga2O3 on-SiC (GaOSiC) substrate. The net carrier concentration of the β-Ga2O3 thin film for GaOSiC substrate was down to about 8% leading to a significantly higher resistivity, compared to the β-Ga2O3 donor wafer, which is attributed to the increase in acceptor-type implantation defects during the ion-cutting process. Furthermore, temperature-dependent current–voltage characteristics suggested that the reverse leakage current was limited by the thermionic emission at a low electric field, while at a high electric field, it was dominated by the Poole–Frenkel emission from E3 deep donors caused by the implantation-induced GaO antisite defects. These results would advance the development of β-Ga2O3 power devices on high thermal conductivity substrate fabricated by ion-cutting technique.

Analysis of barrier inhomogeneities in Ti/p–type strained Si0.95Ge0.05 Schottky diodes using reverse current-voltage characteristics

Extracting electrical parameters such as barrier height inhomogeneities (BHi) from the forward bias can be very challenging in metal/semiconductor (M/Sc) contacts characterized by low barrier height and high series resistance. In this work we demonstrate that the reverse bias characteristics can be used as an efficient alternative method to investigate the inhomogeneity of low barrier height in M/Sc contacts. In particular, the BHi in Ti/p-strained Si0.95Ge0.05 Schottky barrier diodes (SBD) has been investigated using reverse current–voltage-temperature (IR-VR-T) characteristics over the temperature range of 100–300 K. The temperature dependence of the measured barrier heights (ΦRBp) using reverse-bias is successfully explained in terms of a thermionic emission (TE) current transport associated with Gaussian distribution of the barrier height due BHi. The mean homogeneous barrier height (Ф‾RBp) and its corresponding standard deviation (σRs) were determined for different reverse voltages. A decrease in Ф‾RBp and an increase in σRs with increasing reverse bias are observed, indicating a large barrier height distribution upon high applied reverse bias. The deduced average zero-field barrier height (ФFBp≈0.59eV) from IR-VR agrees well with the corresponding value determined from the forward characteristics. Moreover, the reverse bias extracted values for Richardson constant A* based on BHi model, are found in fair agreement with the reported theoretical value of 32 A cm−2 K−2 for our p-type strained Si0.95Ge0.05 alloy. Finally, the results obtained on Pd/n-type Si0.90Ge0.10 structure shown in this work fully support the utilization of such reverse bias method.

High-Performance N-Polar GaN/AlGaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors with Low Surface Roughness Enabled by Chemical–Mechanical-Polishing-Incorporated Layer Transfer Technology

High-Performance N-Polar GaN/AlGaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors with Low Surface Roughness Enabled by Chemical–Mechanical-Polishing-Incorporated Layer Transfer Technology

Reverse‐Current Tolerance for Hydrogen Evolution Reaction Activity of Lead‐Decorated Nickel Catalysts in Zero‐Gap Alkaline Water Electrolysis Systems

AbstractAlkaline water electrolysis (AWE) systems offer a cost‐effective and scalable approach for large‐scale hydrogen production using renewable energy sources. However, their susceptibility to load fluctuations, particularly the reverse‐current (RC) phenomenon during shutdown events, poses a significant challenge to the long‐term stability and scalability of these systems. Herein, a catalytic approach for enhancing the RC tolerance in AWE systems by using Pb‐decorated Ni cathode catalysts (Pb/Ni) is introduced. The oxidation of Pb/Ni by repeated RC lowers the electromotive force for the reverse current operation, and consequently, imparts RC tolerance. Intriguingly, contrary to the expectation that the decoration with lead, an inert material for the hydrogen evolution reaction (HER), will interfere with the hydrogen generation of the Ni catalyst, the presence of Pb on the Ni cathode after the RC flow promotes both the proton desorption and water‐dissociation steps, improving the HER activity. Furthermore, the AWE stack testing with Pb/Ni catalysts is perfectly operated, demonstrating remarkably enhanced RC tolerance during startup/shut‐down (SU/SD) testing protocol. This paper presents a new strategy for mitigating the AWE performance degradation induced by RC flow and for achieving Pb/Ni catalysts with improved operational durability against RC flow in AWE systems.

Post-trench restoration for vertical GaN power devices

The impact of the post-trench restoration on the electrical characteristics of vertical GaN power devices is systematically investigated in this work. Following the achievement of microtrench-free GaN trench structure with modified dry etching conditions, the post-trench tetramethylammonium hydroxide (TMAH)-based wet etching and UV/Ozone-based oxidation process are employed to further refine the trench profile. It is shown that the c-plane trench bottom is restored to the level of unetched surface, as evidenced by the improved Schottky interface. Additionally, the post-trench treatment exhibits the anisotropic characteristics with the preferred rounded corner profile on m-plane sidewall compared to a-plane sidewall. The simulations and experimental results demonstrate that the trench MOS barrier Schottky (TMBS) rectifier based on m-plane sidewall could suppress the electric field crowding at the trench corner and, hence, reduce the reverse leakage current by 1–2 orders of magnitude. Furthermore, the MOSCAP test structures were fabricated on the trenches. The extracted interface trap density (Dit) confirms the effective restoration of trench bottom. However, the sidewall surface exhibits the relatively large Dit, which emphasizes the necessity of optimizing the sidewall, particularly for devices incorporating sidewall channel. The demonstrated post-trench restoration technique improves the surface quality and trench structure for the significantly enhanced electrical performances, which is essential for the development of vertical GaN power devices.

Semi-conductive carbon from industrial tea waste biomass for a p-n junction

AbstractSome semiconducting carbonaceous material was developed from industrial tea waste biomass by catalytic pyrolysis and heteroatom doping; then, a p-n junction was realized on an n-type Si substrate. I-V characteristics of the structures revealed that each structure had a different reverse saturation current, ideality factor, cut-in voltage and series resistance. The variations in the characteristics are attributed to the amorphous and non-uniform nature of the carbonaceous material. Due to the high resistivity of the carbonaceous material, a significant amount of series resistance was present in the characteristics, resulting in very small levels of current that would inhibit the practical use of the structure as a semiconductor diode in electronic circuits.

Facile In-Situ Electrosynthesis of MnO2/RGO Nanocomposite for Enhancing the Electrochemical Performance of Symmetric Supercapacitors

One-pot galvanostatic reverse pulse electrochemical deposition (RPED) was used to create a supercapacitive electrode made of manganese dioxide/reduced graphene oxide (MnO2/RGO) nanocomposite. Systematic changes of two independent parameters of the reverse pulse current, including times of the anodic and cathodic pulses (ta and tc), were investigated to achieve the desired physicochemical and electrochemical properties. Galvanostatic charge–discharge, cyclic voltammetry, and electrochemical impedance spectroscopy tests were employed to perform electrochemical evaluations. According to the results, the MG50-5 nanocomposite, synthesized at ta = 50 ms, tc = 5 ms, and anodic peak current density of 2 mA cm−2, was selected as the optimal sample. This sample showed the highest specific surface area of 284.6 m2 g−1 and the specific capacitance of 789.0 F g−1 at a current density of 0.5 A g−1. The specific capacitances of the MG50-5 symmetric supercapacitor at current densities of 0.5 and 10 A g−1 were 660.14 and 402.50 F g−1, respectively. Maintaining 84.8 % of the specific capacitance after 5000 consecutive cycles at 4 A g−1 indicated stable cycle performance of the MG50-5 symmetric cell. The MG50-5 symmetric supercapacitor presented the maximum energy density of 22.92 Wh kg−1 at a power density of 156.3 W kg−1 and the maximum power density of 3.125 kW kg−1 at an energy density of 13.97 Wh kg−1. Therefore, optimizing reverse pulse current parameters in the galvanostatic RPED of MnO2/RGO nanocomposite leads to an outstanding electrochemical performance of the fabricated supercapacitors.

Spreading of an active region of semi-insulating GaAs detectors after radiation degradation

The radiation hardness of GaAs detectors against high-energy electrons goes up to a few MGy. Their degradation is mainly connected to the decrease of the charge collection efficiency and the increase of the reverse current. On the other hand, an improvement in detection efficiency was observed at low degradation doses. The explanation that this could be caused by an enlargement of the detector active area due to spreading of the collecting electric field caused by radiation-induced defects is studied in this paper. We have used the alpha particles of 241Am, which interact in the GaAs surface layer, to study the enlargement of the detector active region after its degradation by 5 MeV electrons with doses ranging from 24 to 2000 kGy. The results show that the electric field spreads behind the Schottky contact metallization edges not only with increasing applied reverse bias but also with rising cumulative dose of radiation degradation in the dose range from 24 up to 100 kGy, followed by a slight reduction in area size. The electric collecting field keeps larger dimensions than before detector degradation for doses up to 600 kGy. For higher doses than 1000 kGy, the active area of the detector was reduced below its initial size before degradation. Moreover, the improvement of detection efficiency with increasing bias applied becomes weaker with increasing degradation dose. Radiation degradation affects the electric field distribution in semi-insulating GaAs detectors and the results obtained may provide useful knowledge to preparation of multi-pixel GaAs structures for imaging and particle tracking.

In-depth analysis of photovoltaic module parameter estimation

Accurate knowledge of photovoltaic (PV) module model parameters plays an important role in PV power generation system. Therefore, in this study, the single-diode model of PV modules, physical meaning and solution methods of various parameters were introduced firstly. Then, the influence of various parameters on I–V characteristics was analyzed, and the parameter sensitivities of various parameters to the open circuit voltage and short circuit current were quantitatively discussed. Finally, different types of PV modules in a public dataset were used as objects, and different algorithms were employed to estimate the value of each parameter. Through simulation, some important points were provided: (ⅰ) the influence of photocurrent and parallel resistance on I–V characteristics is relatively independent, while the influence of reverse saturation current, series resistance, and ideality factor on I–V characteristics is highly coupled; (ii) the system degrees of freedom is totally different in case of considering the reverse saturation current as a dependent and independent variable. The improvement of the system degrees of freedom remarkably reduces the root mean square error of I–V characteristics; (iii) the estimated parameter resulted from meta-heuristic algorithms do not have the characteristic of uniqueness and may not represent the true values of the parameters.

Adaptation and comparative analysis of HSPICE level‐61 and level‐62 model for a‐IGZO thin film transistors

AbstractThis paper presents a Computer‐aided design (CAD) model for a‐IGZO thin film transistors (TFTs) by adapting SPICE level‐61 RPI a‐Si: H (Hydrogenated Amorphous Silicon) TFT model and level‐62 RPI Poly‐Si (Poly Silicon) TFT model. This work provides a complete understanding of SPICE level‐61 and 62 model parameters, which must be tuned for a‐IGZO TFT simulation. The adapted SPICE models of level‐61 and level‐62 could model all regions of operation of the TFT, that is, above‐threshold and below‐threshold regions. Adapted RPI poly‐Si model also shows the kink effect in ZnO thin film transistors (TFTs) due to the recombination of electron–hole pairs in the channel via boundary trap states present in the poly‐Si TFTs thereby increasing the drain current in the transistors above pinch‐off region. The extracted performance parameters of the adapted models were found to be contiguous with experimental results. The maximum deviation in the subthreshold slope is approximately 5 mV/decade for level‐61 a‐Si TFT, and for level‐62 poly‐Si TFT, deviation in the subthreshold slope is even less, that is, 0.2 mV/decade. The experimental and simulated characteristics, extracted on‐to‐off ratio, negative bias reverse saturation current, and threshold voltage were almost similar. However, an average deviation of 2.4% and 2.27% was observed in the output characteristics of the adapted level‐61 and level‐62 models, respectively.

Comprehensive experimental study on Schottky contact super barrier rectifier

In this paper, on the basis of further discussion of the device structure and operational mechanism of the Schottky contact Super Barrier Rectifier (SSBR), more key experimental results and comparative analysis are added. The experimental results and discussion of the influence of Schottky contact barrier, supper barrier, key cellular parameters and epitaxial layer on device performance are proposed. Both the Schottky contact and super barrier significantly affect forward voltages and reverse leakage currents. However, the influence of the two on forward I–V characteristics is different. The forward voltage and reverse leakage of SSBR have obvious stability as the temperature increases from 20 °C to 150 °C when compared to conventional Schottky Barrier Diode (SBD). Moreover, the forward voltage at small forward current density and high temperature leakage have obvious advantages.

Efficiency and PF Improving Techniques with a Digital Control for Totem-Pole Bridgeless CRM Boost PFC Converters

A totem-pole bridgeless boost converter is one of the most promising topologies for the power factor correction (PFC) stage in high-power applications due to its high efficiency and small number of components. However, due to the totem-pole structure of the field-effect transistor (FET), very high switching loss occurs via the reverse recovery current of the body diode. To solve these problems, critical mode (CRM) control is a good solution to achieve the valley switching technique. With valley switching of CRM control, the switching loss decreases drastically with decreasing turn-on voltage. But, although the CRM control enables valley switching, it is hard to make an exact valley switching control with general zero-voltage detection circuits. In addition, when a frequency limitation scheme is applied to prevent a very high frequency, the switch can operate with hard switching at the boundary of the frequency limitation. Furthermore, the CRM boost PFC has a low PF and high total harmonic distortion (THD) under light-load conditions due to the large negative current resulting from resonance between the inductor and parasitic capacitance. It becomes worse at near-zero input voltage since the resonance current becomes larger near zero-input voltage. Therefore, in this paper, a totem-pole bridgeless boost PFC converter with high efficiency, high PF, and low THD is developed using TMS320F28377 by Texas Instruments. Based on the basic digital structure of the totem-pole bridgeless converter, the proposed controls help with exact valley switching, PF and THD improvement, and frequency limitation. The prototype converter is verified using 90–264 VAC input voltages and 450 V/3.3 kW output specifications.

Simulation and numerical modeling of high performance CH3NH3SnI3 solar cell with cadmium sulfide as electron transport layer by SCAPS-1D

This work includes the numerical modeling (NM) of solar cells consisting of the active layer of CH3NH3SnI3 and electron transport layer of CdS, by employing a software SCAPS-1D. Organic-inorganic lead-based perovskites are superior in terms of power conversion efficiency. However, there are some serious drawbacks associated with them including poor stability, shorter life time and toxicity. Therefore, it is the demand of the hour to explore alternative materials to overcome these shortcomings. In this regard, tin is a competitive alternative to lead because it has similar electronic and chemical properties. Moreover, it is nontoxic, making it environmentally friendly. However, Sn based perovskite devices are reported with inferior power conversion efficacy, to date. In the present work, we have worked on a novel architecture of solar cells containing CH3NH3SnI3 as a light absorber layer and CdS as electron fetching layer. Optimization of the device was performed numerically by varying physical parameters related to the active layer such as thickness, defect density and shallow acceptor concentration. The proposed architecture of solar cells was proved as an efficient system with Jsc of 33.40 mA/cm2, Voc of 0.878 V, FF of 85.25 %, and PCE of 25.02 %. The temperature analysis has revealed that, temperature higher than 300 K increases the reverse saturation current, seriously degrading the structure of the device, hence limiting the power conversion performance of the solar cell. Furthermore, a rear electrode made of the high work function materials like Pt forms an ohmic junction at the HTL/anode interface, enhancing the performance of the device. Results of this study have paved the way for experimentalists to explore opportunities, to rationalize this architecture for real time applications such as inhouse lighting and laptop/smartphone charging.

Reverse-bias current hysteresis at low temperature in GaN Schottky barrier diodes

In this paper, we report an analysis of reverse current mechanisms observed in GaN Schottky barrier diodes leading to hysteretic behavior of the I–V curves at low temperature. By means of DC measurements from 33 to 475 K, we demonstrate the presence of two leakage mechanisms when comparing the experiments with the results obtained using a unified model to predict the ideal reverse current of the diode. Poole–Frenkel emission is the dominant mechanism for temperatures above 200 K, while trap-assisted tunneling prevails for lower temperatures, where also, hysteresis cycles are revealed by means of DC dual-sweep voltage measurements. The energy of the corresponding traps has also been determined, being around 0.2 and 0.45 eV, respectively. The hysteresis phenomenon is attributed to the bias-induced occupancy of the energy states originating the leakage-current processes, which leads to the reduction of the reverse current after a high negative voltage is applied to the diode.

Grid-patterned trench insulated gate bipolar transistor for 1.2 kV hybrid/plug-in hybrid electric vehicle silicon power devices

This paper reports on the newly developed silicon insulated gate bipolar transistor (IGBT) for Toyota’s fifth generation power devices. The designed IGBTs with a grid-patterned trench provide a lower on-state voltage (V ON ) while maintaining a wide mesa width. A successful 15% reduction of V ON was accomplished by enhancement of the two-dimensional hole storage effect. Furthermore, the grid-patterned trench IGBT merged with Schottky and multi-layered anode technology demonstrated a significant improvement in the trade-off curve between the reverse recovery current (I rr ) and V ON in a reverse conducting IGBT without a lifetime control process. As a result, the grid-patterned trench IGBT has contributed to reduce power loss and volume in the new power control units.

Thermal dependence on electrical characteristics of Au/(PVC:Sm2O3)/n-Si structure

In this study, we investigated the current–voltage (I–V) characteristics of Au/n-Si structure with an interfacial layer of Samarium Oxide (Sm2O3) nanoparticles (NPs) in polyvinyl chloride (PVC) matrix within a temperature range of 80–320 K. Applying the thermionic emission (TE) theory, essential electrical parameters such as reverse saturation current (I0), ideality factor (n), zero bias barrier height (ΦB0), series resistance (Rs), and rectification rate (RR) were carefully derived from the I–V data. The mean values of BH and Richardson constant obtained from the modified Richardson plot were determined to be 0.730 eV and 111.4 A/(cmK)2, respectively. Remarkably, this A* value closely matches its theoretical counterpart for n-type Si. Thus, our findings successfully highlight the effectiveness of the thermionic emission (TE) mechanism with the Gaussian distribution of BHs in explaining the I-V-T characteristics of the fabricated Schottky structure, shedding light on the intricate interplay between temperature and diode behavior. These insights offer valuable guidance for designing and optimizing thermal-sensitive devices based on this innovative structure.

Wet chemical poly-Si(n) wrap-around removal for TOPCon solar cells

This work gives an overview on different technological solutions for polysilicon removal in industrial tunnel oxide passivated contact (i-TOPCon) n-type silicon solar cell fabrication. The removal of parasitically deposited poly-Si layers on the front and the edges is a mandatory requirement for a low reverse bias junction leakage current (Irev). A polysilicon removal study on wafer level shows (i) that the efficient removal of the surface oxide layer before poly-Si etching is crucial to achieve short etching times and (ii) that an additive in the KOH solution enhances etching selectivity between poly-Si and silicon oxide surfaces. To evaluate the impact on device level, TOPCon cells have been fabricated in parallel using in-situ n-doped PECVD and LPCVD layers, as well as ex-situ LPCVD poly-Si layers, with another variation of poly-Si removal processes, namely wet chemical inline, wet chemical batch cluster and atmospheric dry etching (ADE). Our results show that a two-minute inline polysilicon removal in hot KOH meets the Irev qualification in case of as deposited in-situ doped layers, whereas for ex-situ doped layers a batch process with a five-minute KOH etching time is needed. LPCVD poly-Si cells show efficiencies above 23%, PECVD poly-Si cells with a batch cluster poly-Si removal process up to 23.4%.

Improvement of performance of perovskite solar cells through BaTiO<sub>3</sub> doping regulated built-in electric field

The preparation of hybrid perovskite solar cells is expensive and environmentally demanding. Carbon-based HTL-free perovskite solar cells (C-PSCs) have attracted much attention because they replace the expensive precious metal electrode and remove the poor stability of the hole transport material. However, the improvement of efficiency is hampered by poor carrier separation and transport performance within C-PSCs, while the enhancement of the built-in electric field can improve the carrier transport performance, thus enhancing photoelectric performance. The built-in electric field can be regulated by doping. The anomalous photovoltaic effect and the built-in electric field of ferroelectric material play an important role in the field of optoelectronics. In this work, a simple and effective method is developed to improve the performance of perovskite solar cells via the combination of internal doping of ferroelectric polymer and external control of electric field. Ferroelectric material barium titanate (BaTiO<sub>3</sub>) powder is added into perovskite precursor solution as an additive to prepare C-PSCs, which can improve the perovskite film morphology, reduce the film defect density, and enhance the carrier transport performance of C-PSCs. The results show that when the addition of BaTiO<sub>3</sub> is 1.0% (mass fraction), the perovskite film is uniform and dense, and the photoelectric conversion efficiency of the cell is the highest. After the forward voltage polarization treatment, the residual polarized electric field of ferroelectric material BaTiO<sub>3</sub> increases the built-in electric field, which provides sufficient power for realizing carrier transport and extraction, thus inhibiting the occurrence of non-radiative recombination. At the same time, the depletion layer width is increased, and the reverse saturation current is reduced, so the cell performance is significantly improved. The optimal device efficiency is 9.02%. This work provides an efficient strategy for regulating the built-in electric field by doping perovskite absorption layer.

Source of IC power consumption and low power design

In these years, with the continuous development of 14nm and 7nm chip processes and the increasing popularity of computers, cell phones, and smart homes, the growing market of electronic products and ultra-fine research for the reliability of the chip requirements gradually increased. The method of reducing power consumption in the new context of new technology is called the chip field die-cut concern. This paper mainly summarizes two aspects of power consumption sources and methods to reduce power consumption, to provide a reference basis for future research directions: First, the major sources of power consumption are static power consumption and dynamic power consumption. The primary sources of static power consumption are sub-threshold leakage and gate leakage current. This paper also mentions some other leakage currents, such as reverse bias PN junction current and induced leakage current, which can be more carefully considered when exploring methods to reduce power consumption. A more comprehensive consideration when exploring ways to reduce power consumption. Dynamic power consumption is mainly divided into Switching power and Internal power and short-circuit power. Then we summarize the existing methods which can reduce power consumption: Clock gating (including Clock gating without a latch and Clock gating with a latch), Dynamic voltage and frequency scaling, multi-supply and multi-voltage technology, Power gating and multi-threshold voltage. These methods are from a proprietary perspective to reduce power consumption.