Retention Errors Research Articles

CeSR + Assisted LDPC: A Holistic Strategy to Improve MLC NAND Flash Reliability

NAND flash suffers from program interference and retention errors, which negatively affect its reliability. Existing schemes preprocess raw data before writing them to reduce Raw Bit Error Rate (RBER) and leverage ECCs (such as LDPC codes) to reduce Uncorrectable Bit Error Rate (UBER). Prior arts failed to take into account the counteractions between the program interference and retention errors.Thus, they may lead to sub-optimal error avoidance. Besides, after the preprocessing procedure, data randomness may be affected. Since NAND flash shows numerical-correlated error characteristics, there's a potential to provide such information to LDPC codes to further improve performance. In this article, we propose a holistic strategy consisting of two coupled procedures to enhance flash reliability. First, we use our previously proposed CeSR strategy to reduce RBER. Second, we improve the existing LDPC codes and name it Assisted LDPC strategy to reduce UBER. The Assisted LDPC is deeply coupled with CeSR. It leverages the data pattern after CeSR to improve the decoding success rate and accelerate the decoding procedure. The evaluation shows that compared with the state-of-the-art NRC strategy, CeSR can reduce the RBER of hot and cold data by up to 20.30% and 85.13%, respectively. Besides, compared with the traditional LDPC, the Assisted LDPC decoding strategy can increase the decoding success rate by up to 97% for cold data and reduce the average decoding iteration number of MSB pages for hot and cold data by up to 31.6% and 73.9%, respectively.

Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design

For some applications, errors have a different impact on data and memory systems depending on whether they change a zero to a one or the other way around; for an unsigned integer, a one to zero (or zero to one) error reduces (or increases) the value. For some memories, errors are also asymmetric; for example, in a DRAM, retention failures discharge the storage cell. The tolerance of such asymmetric errors can result in a robust and efficient system design. Error Control Codes (ECCs) are one common technique for memory protection against these errors by introducing some redundancy in memory cells. In this paper, the asymmetry in the errors in Embedded DRAMs (eDRAMs) is exploited for error-tolerant designs without using any ECC or parity, which are redundancy-free in terms of memory cells. A model for the impact of retention errors and refresh time of eDRAMs on the False Positive rate or False Negative rate of some eDRAM applications is proposed and analyzed. Bloom Filters (BFs) and read-only or write-through caches implemented in eDRAMs are considered as the first case studies for this model. For BFs, their tolerance to some zero to one errors (but not one to zero errors) is combined with the asymmetry of retention errors in eDRAMs to show that no ECC or parity is needed to protect the filter; moreover, the eDRAM refresh time can significantly be increased, thus reducing its power consumption. For caches, this paper shows that asymmetry in errors can be exploited also by using a redundancy-free error-tolerant scheme, which only introduces false negatives, but no false positives, therefore causing no data corruption. The proposed redundancy-free implementations have been compared with existing schemes for BFs and caches to show the benefits in terms of different figures of merit such as memory size, area, decoder/encoder complexity and delay. Finally, in the last case study, we show that the asymmetry of retention errors can be used to develop additional error correction capabilities in Modular Redundancy Schemes.

Proton-induced single-event effect and influence of annealing on multiple feature size NAND flash memory

The proton-induced single-event effect sensitivity of multiple feature size NAND flash memories has been studied. The single-event upset cross section of memories was obtained as a function of feature size, and the cross section of device increases significantly with increasing integration. Monitoring of the proton-irradiated devices for up to 2 months indicates that the retention errors of devices due to reduced insulating properties of the tunnel oxide layer are more critical than error annealing due to the annealing of the trapped charge. During the dynamic test, a large number of semipermanent and regular data “stuck bit” errors were captured, which disappeared after a few days of annealing. Micro-dose effect, which occurred in the external control circuit of NAND flash by proton-produced secondary particles, is considered responsible to the “stuck bit” errors.

Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems

Abstract Three-dimensional (3D) NAND flash memory-based solid state drives (SSDs) have been widely adopted in cyber-physical systems, due to its performance benefits and scalability. Although 3D flash rapidly increases storage capacity by stacking flash cells in the vertical direction, it faces severe retention errors as well. Periodic refreshing, while effectively mitigating the retention issues, seriously degrades the storage performance and the endurance of 3D NAND flash memory. To address the above challenge, we propose partial-refresh (PR), a novel lightweight data refresh scheme for 3D NAND flash memory in cyber-physical systems. PR leverages LDPC detectability to identify cells that are more vulnerable to errors. By moving these susceptible bits to new pages, PR avoids copying an entire page, and reduces the refresh cost and prolongs the SSD lifetime. Our experimental results show that, on average, a PR-aware flash memory improves refresh performance by 28.2% and extends the SSD lifetime by 4.6% over the state-of-the-art while preserving the high data reliability.

SREA: A self-recovery effect aware wear-leveling strategy for the reliability extension of NAND flash memory

With aggressive scaling and multilevel cell technology, the reliability and lifetime of the NAND flash degrades. To address this issue, a Self-Recovery Effect Aware (SREA) strategy is proposed to extend the storage reliability of the NAND flash. The key purpose of SREA is a wear-leveling strategy based on the self-recovery effect of the NAND flash. First, this study verifies the self-recovery effect of the NAND flash based on our hardware-software codesigned experimental platform; then, we propose the concept of relaxation time (tr). The change rule of the data retention error under different degrees of tr for blocks subjected to different program/erase (P/E) cycles is also investigated. The experimental results show that there is an approximately 60% gap of retention error rate when tr = 0 h and tr = 6 h after the same retention time. In addition, we apply the experimental rules to the wear-leveling strategy. Compared with the traditional wear-leveling strategy that does not consider tr, the maximum data reliable retention time of SREA can be extended by 2.67×.

Heavy-ion induced radiation effects in 50 nm NAND floating gate flash memories

Using the 86Kr, 129Xe and 209Bi ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the short-term and long-term radiation effects induced by heavy ions induced in 50 nm NAND floating gate (FG) flash memories are investigated. The linear energy transfer (LET) value covers the range from 20.7 to 99.8 MeV·cm2/mg. Only upset errors in FG cells are observed due to that the flash memories are powered off and the peripheral circuitries are shielded during heavy ion irradiation. The errors in FG cells irradiated with ions of different LET values are decreasing with time under room temperature condition. After the reprogramming of flash memories, retention errors in FG cells are observed in some flash memories, which are irradiated by heavy ions with LET values greater than 37.6 MeV·cm2/mg. The dependence of single event upset, annealing of errors and retention errors in FG cells on the ion LET value is analysed and the underlying mechanisms are discussed.

On the distribution of the threshold voltage in multi-level cell flash memories

In Multi-Level Cell (MLC) memories, multiple bits of information are packed within the cell to enable higher capacity and lower cost of manufacturing compared to those of the single-level cell flash. However, because of heavy information packing, MLC memories suffer from several error sources including inter-cell interference, retention error, and random telegraph noise which make their lifetime shorter. Having so many error sources that are statistically hard to characterize makes it challenging to properly derive the underlying probability distribution of the sensed threshold voltage, which is vital for finding optimal decision rules to secure better detection performance and hence better lifetime. Although several recent works have already considered this problem, they mostly recourse to few loose assumptions that are far from being realistic. In this study, a more comprehensive/general analysis is conducted to derive the probability density function of the final sensed voltage, and through realistic simplifications, closed form expressions are presented. Extensive computer simulations corroborate the accuracy of the derived analytical expressions, and we think they shall be essential for accurately estimating the reliability and the overall lifetime of modern MLC memories.

Development and evaluation of a plastic scintillating resin for radioactive tin determination

In the next few years, a large number of nuclear facilities will be closed. This will involve the measurement of large amounts of nuclear wastes during the decommissioning process. This large amount of samples to be decommissioned will require the use of rapid and economical techniques. In this sense, PS resins appear as a good option since they unify separation and measurement preparation in a single step, reducing time and reagents. The objective of this study was to develop a PS resin for the measurement of radioactive tin, especially 126Sn, one of the main responsible of the dose in the future. The study optimizes the PS resin preparation (TBP is used as the extractant, Crosslinked plastic scintillator as the support and an 80% extractant solution for the impregnation) and the tin separation medium (2 M HCl) from described interferences. The detection efficiency was established using a calibration based on the radionuclide energy. Finally, a real sample, coming from the reprocessing of fission products, was analyzed obtaining quantitative retention and quantification errors lower than 5%.

Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

A recent large-scale study revealed that the uncorrectable bit error rates in data center solid-sate drives (SSDs) may fall far below the JEDEC standard recommendations. Here, a new refresh policy is proposed to improve the tolerated raw bit error rate (RBER) based on the observation that (a) a small ratio of SSD units may have a much higher RBER than the rest and (b) the RBER is dominated by the retention error rate. An approach is used to estimate the remaining retention time, i.e., the reliable data storage time, of flash memory pages. This estimation can be performed each time a memory page is read based on the number of detected retention errors and the elapsed time since data was programmed or refreshed. The fact that the estimated remaining retention time is smaller than a maximum time interval before the next page access is an indication that data needs to be refreshed. It is estimated that the tolerated retention RBER can be increased by up to 35× over a storage period of 3 years if the stored data are checked on a monthly basis and refreshed only if necessary. The proposed technique has the ability to adapt the average time between refresh operations to the actual RBER. Maximum refresh time reductions of about 12× are reported as compared to systematic refresh schemes.

Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data

DRAM refresh is responsible for significant performance and energy overheads in a wide range of computer systems, from mobile platforms to datacenters [1] . With the growing demand for DRAM capacity and the worsening retention time characteristics of deeply scaled DRAM, refresh is expected to become an even more pronounced problem in future technology generations [2] . This paper examines content aware refresh , a new technique that reduces the refresh frequency by exploiting the unidirectional nature of DRAM retention errors: assuming that a logical 1 and 0 respectively are represented by the presence and absence of charge, 1 -to- 0 failures are much more likely than 0 -to- 1 failures. As a result, in a DRAM system that uses a block error correcting code (ECC) to protect memory, blocks with fewer 1 s can attain a specified reliability target (i.e., mean time to failure) with a refresh rate lower than that which is required for a block with all 1 s. Leveraging this key insight, and without compromising memory reliability, the proposed content aware refresh mechanism refreshes memory blocks with fewer 1 s less frequently. To keep the overhead of tracking multiple refresh rates manageable, refresh groups—groups of DRAM rows refreshed together—are dynamically arranged into one of a predefined number of refresh bins and refreshed at the rate determined by the ECC block with the greatest number of 1 s in that bin. By tailoring the refresh rate to the actual content of a memory block rather than assuming a worst case data pattern, content aware refresh respectively outperforms DRAM systems that employ RAS-only Refresh, all-bank Auto Refresh, and per-bank Auto Refresh mechanisms by 12, 8, and 13 percent. It also reduces DRAM system energy by 15, 13, and 16 percent as compared to these systems.

Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation

Multilevel cell (MLC) states with lower threshold voltage endure less cell damage, lower retention error, and less current consumption. Based on these characteristics, it is opportunistic to strengthen MLC flash by introducing bit-flipping that reshapes state proportions on MLC pages. In this paper, we present a holistic study of bit-flipping schemes upon MLC flash in theory and practice. Specifically, we systematically investigate effective bit-flipping schemes and propose four new schemes on manipulating MLC states. We further design a generic implementation framework, named MLC bit-flipping framework, to implement bit-flipping schemes within solid state drives controllers, nicely integrating with existing system-level optimizations to further improve overall performance. The experimental results demonstrate that our proposed bit-flipping schemes standalone can reduce up to 28% cell damages and 53% retention errors. Our circuit-level simulation manifests that the bit-flipping latency on a page is less than 4 $\mu \text{s}$ when using 8K logic gates.

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell. Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

Influences of total ionizing dose on single event effect sensitivity in floating gate cells**Project supported by the National Natural Science Foundation of China (Grant Nos. 11690041, 11675233, U1532261, and 11505243).

The influences of total ionizing dose (TID) on the single event effect (SEE) sensitivity of 34-nm and 25-nm NAND flash memories are investigated in this paper. The increase in the cross section of heavy-ion single event upset (SEU) in memories that have ever been exposed to TID is observed, which is attributed to the combination of the threshold voltage shifts induced by γ-rays and heavy ions. Retention errors in floating gate (FG) cells after heavy ion irradiation are observed. Moreover, the cross section of retention error increases if the memory has ever been exposed to TID. This effect is more evident at a low linear energy transfer (LET) value. The underlying mechanism is identified as the combination of the defects induced by γ-rays and heavy ions, which increases the possibility to constitute a multi-trap assisted tunneling (m-TAT) path across the tunnel oxide.

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Compared to planar NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory. Our goal is to (1)~identify and understand these new error characteristics of 3D NAND flash memory, and (2)~develop new techniques to mitigate prevailing 3D NAND flash errors. \chIIIn this paper, we perform a rigorous experimental characterization of real, state-of-the-art 3D NAND flash memory chips, and identify three new error characteristics that were not previously observed in planar NAND flash memory, but are fundamental to the new architecture of 3D NAND flash memory. \beginenumerate [leftmargin=13pt] ıtem 3D NAND flash memory exhibits layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different. We are the first to provide detailed experimental characterization results of layer-to-layer process variation in real flash devices in open literature. Our results show that the raw bit error rate in the middle layer can be 6× the error rate in the top layer. ıtem 3D NAND flash memory experiences \emphearly retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming, but then increases at a much slower rate. We are the first to perform an extended-duration observation of early retention loss over the course of 24~days. Our results show that the retention error rate in a 3D NAND flash memory block quickly increases by an order of magnitude within $\sim$3 hours after programming. ıtem 3D NAND flash memory experiences retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells. Our results show that charge leaks at a lower rate (i.e., the retention loss speed is slower) when the neighboring cell is in a state that holds more charge (i.e., a higher-voltage state). \endenumerate Our experimental observations indicate that we must revisit the error models and error mitigation mechanisms devised for planar NAND flash, as they are no longer accurate for 3D NAND flash behavior. To this end, we develop \emphnew analytical model\chIs of (1)~the layer-to-layer process variation in 3D NAND flash memory, and (2)~retention loss in 3D NAND flash memory. Our models estimate the raw bit error rate (RBER), threshold voltage distribution, and the \emphoptimal read reference voltage (i.e., the voltage at which RBER is minimized when applied during a read operation) for each flash page. Both models are useful for developing techniques to mitigate raw bit errors in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, LaVAR, reduces process variation by fine-tuning the read reference voltage independently for each layer. Our second technique, LI-RAID, improves reliability by changing how pages are grouped under the RAID (Redundant Array of Independent Disks) error recovery technique, using information about layer-to-layer process variation to reduce the likelihood that the RAID recovery of a group could fail significantly earlier during the flash lifetime than recovery of other groups. Our third technique, ReMAR, reduces retention errors in 3D NAND flash memory by tracking the retention age of the data using our retention model and adapting the read reference voltage to data age. Our fourth technique, ReNAC, adapts the read reference voltage to the amount of retention interference to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash manufacturer wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%. For more information on our new experimental characterization of modern 3D NAND flash memory chips and our proposed models and techniques, please refer to the full version of our paper~\citeluo.pomacs18.

Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories

DRAM density scaling has become increasingly difficult due to challenges in maintaining a sufficiently high storage capacitance and a sufficiently low leakage current at nanoscale feature sizes. Non-volatile memories (NVMs) have drawn significant attention as potential DRAM replacements because they represent information using resistance rather than electrical charge. Spin-torque transfer magnetoresistive RAM (STT-MRAM) is one of the most promising NVM technologies due to its relatively low write energy, high speed, and high endurance. However, STT-MRAM suffers from its own scaling problems. As the size of the storage element decreases with technology scaling, STT-MRAM retention error rates are expected to increase, which will require multi-bit error-correcting code (ECC) and periodic scrubbing. We introduce the Sanitizer architecture, which mitigates the performance and energy overheads of ECC and scrubbing in future STT-MRAM based main memories. To reduce the scrubbing rate, a coarse-grained, multi-bit ECC mechanism with a 12.5 percent storage overhead is used. To avoid fetching multiple blocks from memory and performing costly ECC checks on every read, the memory regions that will likely be accessed in the near future are predicted and proactively scrubbed. Compared to a conventional STT-MRAM system, Sanitizer improves performance by 1.22 $\times$ and reduces end-to-end system energy by 22 percent.

A joint-LDPC decoding scheme based on retention error characteristics for MLC NAND flash memory

With the aggressive scaling and the Multi-Level Cell (MLC) technology, the reliability of NAND flash degrades seriously. Therefore, the traditional error correction schemes are becoming less and less effective. Low-Density Parity-Check (LDPC) code and soft-decision memory sensing will be more suitable in the next generation Error Correction Code (ECC) technologies for MLC NAND flash memory. However, LDPC ECC schemes have their own bottleneck due to the unacceptably long read latency during the decoding scheme. The read latency primarily includes two aspects: repeated read cycles and iterative belief-propagation decoding. Motivated by the precise probability information can improve the performance of LDPC decoding, we propose a novel Joint-LDPC (J-LDPC) scheme to reduce the decoding latency of LDPC ECC. The key idea of the proposed J-LDPC scheme is to introduce a new calculating method of probability information in a pair of shared flash pages, according to the retention error characteristics of MLC NAND flash rather than several reading operations. Through a large amount of experiments from our own hardware-software co-designed experimental platform, compared with the traditional soft-decision LDPC scheme, the proposed J-LDPC scheme can reduce the average iterations of LDPC decoder by 50% and enhance the error correction strength by 58%.

Improving the reliability of chip-off forensic analysis of NAND flash memory devices

Digital forensic investigators often need to extract data from a seized device that contains NAND flash memory. Many such devices are physically damaged, preventing investigators from using automated techniques to extract the data stored within the device. Instead, investigators turn to chip-off analysis, where they use a thermal-based procedure to physically remove the NAND flash memory chip from the device, and access the chip directly to extract the raw data stored on the chip.We perform an analysis of the errors introduced into multi-level cell (MLC) NAND flash memory chips after the device has been seized. We make two major observations. First, between the time that a device is seized and the time digital forensic investigators perform data extraction, a large number of errors can be introduced as a result of charge leakage from the cells of the NAND flash memory (known as data retention errors). Second, when thermal-based chip removal is performed, the number of errors in the data stored within NAND flash memory can increase by two or more orders of magnitude, as the high temperature applied to the chip greatly accelerates charge leakage. We demonstrate that the chip-off analysis based forensic data recovery procedure is quite destructive, and can often render most of the data within NAND flash memory uncorrectable, and, thus, unrecoverable.To mitigate the errors introduced during the forensic recovery process, we explore a new hardware-based approach. We exploit a fine-grained read reference voltage control mechanism implemented in modern NAND flash memory chips, called read-retry, which can compensate for the charge leakage that occurs due to (1) retention loss and (2) thermal-based chip removal. The read-retry mechanism successfully reduces the number of errors, such that the original data can be fully recovered in our tested chips as long as the chips were not heavily used prior to seizure. We conclude that the read-retry mechanism should be adopted as part of the forensic data recovery process.

Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM

This paper proposes the Active Precharge Hammering on a Row (APHR) test to evaluate displacement damage (DD) in 3x-nm DRAM components. Irradiated SDRAM devices could have multiple current leakage paths, partly owing to DD effects. The degree of leakage from cells with DD can be differentiated from undamaged cells by the difference in the number of hammered accesses to the two types of cells. Proton-based SER tests were performed with DDR3 SDRAM components made using 3x-nm technologies. The experimental results showed that bit errors caused by the APHR test (APHR errors) were more than five times higher in the irradiated sample compared to the non-irradiated sample, and APHR errors were not detectable within 64-ms retention time using the traditional retention test method. In the worst case, the number of hammerings required to cause an APHR error in the irradiated sample reduced by 36 times compared to that in the non-irradiated sample even after the irradiated sample was annealed at 150° C so as to have no retention errors within the maximum retention time of 64-ms.

NRC: A Nibble Remapping Coding Strategy for NAND Flash Reliability Extension

According to the appearance frequency of nibble short code, this paper presents a novel nibble remapping coding (NRC) strategy to increase the ratio of “1”s in the programming data of NAND flash memory. Because the NRC strategy does not change the length of data during encoding and decoding process, it does not consume any extra user data area of NAND flash. In addition, it can be transparently fit within the flash translation layer algorithms. The experimental results show that the NRC strategy reduces the program disturb errors by 56.9% and decreases the data retention errors by 52.5%, while experiencing only 2.2% degradation in writing speed and 3.2% degradation in reading speed. Compared with conventional BCH code, NRC can significantly enhance the efficacy of the out-of-band space to improve the storage reliability.

Optimizing Latency, Energy, and Reliability of 1T1R ReRAM Through Cross-Layer Techniques

Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM in main memory. The 1-transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ReRAM cross-point array. However, 1T1R ReRAM array has significantly lower lifetime compared to a DRAM array. In this paper, we show how cross-layer techniques can be used to improve reliability of 1T1R array with minimum latency and energy cost. At the circuit level, we show how voltage settings (pulse amplitude and pulse width) of word-line (WL), bit-line (BL), and source-line (SL) can be used to lower latency, lower energy consumption and improve reliability. We also show how appropriate choice of voltage settings can help reduce retention and endurance errors while minimizing energy. At the architecture level, we propose a new bit-flipping scheme that helps reduce the Bit Error Rate (BER) even further. We show how application of circuit-level and architecture-level techniques makes it possible to achieve a lifetime of 10 years with a simple BCH (t=2) code. Finally, we evaluate the system-level performances of a 1GB ReRAM and 1GB DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the proposed ReRAM based main memory can improve Instruction Per Cycle (IPC) by 5.2% and energy by up to 72% compared to a DRAM memory system.