Retention Errors Research Articles

PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash

With aggressive scaling and multilevel cell technology, the reliability of NAND flash continuously degrades. The lifetime of NAND flash is highly restricted by the bit error rate (BER), and error-correcting codes (ECCs) can provide only limited error correction capability to tolerate increasing bit errors. To cope with this issue, a novel page endurance variance aware (PEVA) strategy is proposed to extend the lifetime of NAND flash based on the experimental observations from our hardware–software codesigned experimental platform. The experimental observations indicate that the BER distribution of retention error shows distinct variances in different pages. The key purpose of PEVA is to exploit the lifetime potency of every page in a block by introducing fine-grained bad page management instead of coarse-grained bad block management (BBM). The experimental results show that the PEVA can extend the lifetime of $2\times $ -nm NAND flash by $9.8\times $ compared with the conventional BBM and that there is at most an 8.7% degradation in writing speed compared with the traditional sector mapping technology. In addition, the maximum writing response time increased by at most 5.9% during the operation of the PEVA strategy.

A page-granularity wear-leveling (PGWL) strategy for NAND flash memory-based sink nodes in wireless sensor networks

Sink nodes are the data centers of wireless sensor networks (WSNs), and the storage management scheme for such nodes is vital, particularly in applications such as wireless multimedia sensor networks that involve the collection of massive amounts of data. NAND flash memory is often employed in sink nodes because of its excellent characteristics. Because the lifetime of NAND flash memory is highly restricted by the bit error rate (BER), we present a novel page-granularity wear-leveling (PGWL) strategy to extend the lifetime of NAND flash memory. The concept of PGWL is motivated by two main experimental observations obtained from our own experimental platform for NAND flash memory: first, the raw bit error rate (RBER) distribution exhibits a distinct variance in endurance among different pages, and this variance is more significant than that among different blocks; second, programming relief operations (consisting of only erasing, not programming) can clearly reduce both program-disturb and retention errors. In this study, we first present a practical average RBER prediction model to evaluate the reliability of flash pages using the system clock of the sink node. Thus, the PGWL strategy enables self-adaptive leveling of the RBER growths of different pages in real time by introducing page-granularity wear leveling instead of block-granularity wear leveling to exploit the lifetime potency of each page in a block. Experimental results show that PGWL can extend the lifetime of 2×-nm NAND flash memory by 88.3% compared with traditional bad block management (BBM), while experiencing at most a 0.85% degradation in data throughput speed compared with the conventional sector mapping scheme.

LSB page refresh based retention error recovery scheme for MLC NAND Flash

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

A cross layer approach for efficient thermal management in 3D stacked SoCs

3D stacking of silicon dies via Through Silicon Vias (TSVs) is an emerging technology to increase performance, energy efficiency and integration density of today's and future System-on-Chips (SoCs). Especially the stacking of Wide I/O DRAMs on top of a logic die is a very promising approach to tackle the memory wall and energy efficiency challenge. The potential of this type of stacking is currently under investigation by many research groups and companies in particular for mobile devices. There, for instance, the baseband processing and the application processor can be implemented on the same single logic die. On top of this die one or several Wide I/O DRAMs are stacked. An example of such a SoC is the WIOMING chip [15]. However, new challenges emerge, especially thermal management, which is already a very demanding challenge in current 2D SoCs. With 3D SoCs this problem exacerbates due to reliability issues such as the temperature sensitivity of DRAMs, i.e., the retention time of a DRAM cell largely decreases with increasing temperature.In this paper, we show a holistic cross layer reliability approach for efficient reliability management starting from measuring and modeling of DRAM retention errors, which finally leads to optimizations for specific applications. These optimizations exploit the data lifetime and the inherent error resilience of the application, which is for instance given in the probabilistic behavior of wireless communications.

SECRET

DRAMs are used as the main memory in most computing systems today. Studies show that DRAMs contribute to a significant part of overall system power consumption. One of the main challenges in low-power DRAM design is the inevitable refresh process. Due to process variation, memory cells exhibit retention time variations. Current DRAMs use a single refresh period determined by the cell with the largest leakage. Since prolonging refresh intervals introduces retention errors, a set of previous works adopt conventional error-correcting code (ECC) to correct retention errors. However, these approaches introduce significant area and energy overheads. In this article, we propose a novel error correction framework for retention errors in DRAMs, called SECRET (selective error correction for refresh energy reduction). The key observations we make are that retention errors are hard errors rather than soft errors, and only few DRAM cells have large leakage. Therefore, instead of equipping error correction capability for all memory cells as existing ECC schemes, we only allocate error correction information to leaky cells under a refresh interval. Our SECRET framework contains two parts: an offline phase to identify memory cells with retention errors given a target error rate and a low-overhead error correction mechanism. The experimental results show that among all test cases performed, the proposed SECRET framework can reduce refresh power by 87.2% and overall DRAM power up to 18.57% with negligible area and performance overheads.

Word line program disturbance based data retention error recovery strategy for MLC NAND Flash

NAND Flash has been widely used as storage solutions for portable system due to improvement on data throughput, power consumption and mechanical reliability. However, NAND Flash presents inevitable decline in reliability due to scaling down and multi-level cell (MLC) technology. High data retention error rate in highly stressed blocks causes a trend of stronger ECC deployed in system, with higher hardware overhead and spare bits cost. In this paper, a word line program disturbance (WPD) based data retention error recovery strategy, which induces extra electron injection to compensate floating gate electron leakage during long retention time, is proposed to reduce the data retention error rate and improve the retention reliability of highly scaled MLC NAND Flash memories. The proposed strategy is applied on 2×-nm MLC NAND Flash and the device one-year retention error rate after 3K, 4K, 5K and 6K P/E cycled decreases by 75.7%, 79.3%, 82.3% and 83.3%, respectively.

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells

This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.

Guidewire retention following central venous catheterisation: a human factors and safe design investigation.

Central Venous Catheterisation (CVC) has occasionally been associated with cases of retained guidewires in patients after surgery. In theory, this is a completely avoidable complication; however, as with any human procedure, operator error leading to guidewires being occasionally retained cannot be fully eliminated. The work described here investigated the issue in an attempt to better understand it both from an operator and a systems perspective, and to ultimately recommend appropriate safe design solutions that reduce guidewire retention errors. Nine distinct methods were used: observations of the procedure, a literature review, interviewing CVC end-users, task analysis construction, CVC procedural audits, two human reliability assessments, usability heuristics and a comprehensive solution survey with CVC end-users. The three solutions that operators rated most highly, in terms of both practicality and effectiveness, were: making trainees better aware of the potential guidewire complications and strongly emphasising guidewire removal in CVC training, actively checking that the guidewire is present in the waste tray for disposal, and standardising purchase of central line sets so that differences that may affect chances of guidewire loss is minimised. Further work to eliminate/engineer out the possibility of guidewires being retained is proposed.

Potential Prevention and Treatment of Maifanite for Alzheimer's Disease Based on Behavior Test, Oxidative Stress Assay, and Trace Element Analysis in Hippocampus of Aβ(25–35)-Induced AD Rats

This study aimed to assess whether maifanite can improve the learning and memory, and antioxidant abilities of Alzheimer's disease (AD) rats. The 70 rats were divided into seven groups: [A] normal control group, [B] AD model group, [C] sham group, [D] positive control group (donepezil), [E] low-dose maifanite group, [F] middle-dose maifanite group, [G] high-dose maifanite group. For [B], [D], [E], [F], and [G] groups, Aβ(25-35) ventricle injection was carried out, then respective medicine were administered once a day for 60 consecutive days. The step-down and step-through test were used to measure learning and memory ability. The hippocampus levels of superoxide dismutase (SOD), glutathione peroxidase (GSH-Px), and malondialdehyde (MDA) were assayed. The hippocampus contents of Al, Fe, Cu, Zn, Se, and Mn were analyzed by inductively coupled plasma-atomic emission spectrometer. Maifanite decreased the acquisition errors and the retention errors while prolonging the step-down latency, and decreased the number of electric shocks while prolonging the first latency of AD rats. Aβ(25-35) ventricle injection initiated the decrease of SOD and GSH-Px activities and the increase of MDA content, and triggered the rise of Al, Fe, and Cu levels and the decline of Mn, Zn, and Se levels. The SOD and GSH-Px activities were enhanced followed by reduced MDA level, and the levels of Mn, Zn, and Se increased accompanied by Al, Fe, and Cu decreased in the maifanite treat groups. Maifanite could improve the learning and memory, and the antioxidant abilities of AD rats. Maifanite had the potential prevention and treatment for AD.

Degradation of Sub 40-nm NAND Flash Memories Under Total Dose Irradiation

We study total dose effects in advanced multi- and single-level NAND Flash memories. We discuss retention and functional failures, analyzing the role of floating gate cells and peripheral circuitry, as compared to previous generations. We found that in these new devices, retention errors appear in all program levels. Guidelines on worst-case testing conditions are given.

Retention Errors in 65-nm Floating Gate Cells After Exposure to Heavy Ions

The retention of floating gate cells is studied up to one year after heavy-ion exposure, without using accelerated tests. Cross-sections of retention errors and threshold voltage shifts are discussed and compared with previous generation devices. The dependence of retention errors on the program level and irradiation angle is discussed and the underlying mechanisms are examined.

Quasi-Cross Lattice Tilings With Applications to Flash Memory

We consider lattice tilings of ℝn by a shape we call a (k+, k-, n)-quasi-cross. Such lattices form perfect error-correcting codes which correct a single limited-magnitude error with prescribed maximal-magnitudes k+ and k- of positive error and negative error respectively (the ratio of which, β = k-/k+, is called the balance ratio). These codes can be used to correct both disturb and retention errors in flash memories, which are characterized by having limited magnitudes and different signs. For any rational 0 <; β <; 1 we construct an infinite family of (k+, k-, n)-quasi-cross lattice tilings with balance ratio k-/k+ = β. We also provide a specific construction for an infinite family of (2,1, n) -quasi-cross lattice tilings. The constructions are related to group splitting and modular B1 sequences. In addition, we study bounds on the parameters of lattice-tilings by quasi-crosses, and express them in terms of the arm lengths of the quasi-crosses and the dimension. We also prove constraints on group splitting, a specific case of which shows that the parameters of the lattice tiling by (2, 1, n)-quasi-crosses are the only ones possible for these quasi-crosses.

Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming

Highly reliable and low power solid-state drive (SSD) is proposed. Through the analysis based on measured error rate in the SSDs with NAND flash memories, the memory cell error shows the asymmetric characteristic in multilevel cell (MLC) NAND flash memories. The proposed asymmetric coding increases the number of “1” s or “0” s of the programming data to reduce the data retention error. The numbers of the memory cells in the higher <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> states are reduced. The memory cell error is reduced by 90% with the asymmetric coding. On the other hand, the inter bit-line capacitance significantly increases with the scaling of memory cells. The bit-line charging current becomes unacceptably large. To decrease the write power consumption, the stripe pattern elimination algorithm (SPEA) is proposed. The SPEA eliminates the column-stripe pattern which consumes the maximum power to charge all of the inter bit-line capacitance in a NAND chip. Theoretical analyses are given for both the asymmetric coding and the SPEA. The asymmetric coding and the SPEA can be used together with the other highly reliable or low power techniques such as intelligent interleaving and adaptive code selection scheme and realizes the high reliability and low power consumption.

Evaluation of Relevant Time-of-Flight-MS Parameters Used in HPLC/MS Full-Scan Screening Methods for Pesticide Residues

An automatic screening method based on HPLC/time-of-flight (TOF)-MS (full scan) was used for the analysis of 103 non-European fruit and vegetable samples after extraction by the quick, easy, cheap, effective, rugged, and safe method. The screening method uses a database that includes 300 pesticides, their fragments, and isotopical signals (910 ions) that identified 210 pesticides in 78 positive samples, with the highest number of detection being nine pesticides/sample. The concentrations of 97 pesticides were <10 microg/kg, 53 were between 10 and 100 microg/kg, and 60 were at a concentration of >100 microg/kg. Several parameters of the automatic screening method were carefully studied to avoid false positives and negatives in the studied samples; these included peak filter (number of chromatographic peak counts) and search criteria (retention time and error window). These parameters were affected by differences in mass accuracy and sensitivity of the two HPLC/TOF-MS systems used with different resolution powers (15 000 and 7500), the capabilities of which for resolving the ions included in the database from the matrix ions were studied in four matrixes, viz., pepper, rice, garlic, and cauliflower. Both of these mass resolutions were found to be satisfactory to resolve interferences from the signals of interest in the studied matrixes.

Structure Processing of Web-Based Menus

Grounded in cognitive load theory, levels of processing theory, modes of learning research, and the facets of working memory (WM) framework, the primary goal of this investigation was to seek empirical evidence for a structure processing mechanism in WM that facilitates the coordination of associations made into coherent structures and the role this mechanism might play in performance and retention. This goal was motivated by a gap in the understanding of mental model production and encoding processes in WM. To carry out this goal, two usability studies were conducted to investigate retention, error, and time performance of Web-based menus created with structured or unstructured design. Relationships between these measures and coordination ability in WM, as well as storage and supervision ability, were also assessed. In Study 1, which tested simple Web-based menus, correlations of .28, −.56, and −.54 were detected between coordination (CC) and retention scores, CC and errors, and CC and time; in Study 2, which tested commercial Web-based menus, correlations of .46, −.45, and −.25 were detected. For Studies 1 and 2, differences in favor of structured design for retention, error, and time performance were highly significant (p < .001).

The association between refractive cutoffs for spectacle provision and visual improvement among school-aged children in South Africa

Objectives:To evaluate different refractive cutoffs for spectacle provision with regards to their impact on visual improvement and spectacle compliance.Design:Prospective study of visual improvement and spectacle compliance.Participants:South African school children aged...

Covert muscle excitation is outflow from the central generation of motor imagery

Two studies were conducted in an attempt to examine inflow and outflow processing by examining covert muscle excitation during motor imagery (MI) and its correlation with motor task performance. Examining 80 novice dart throwers in Experiment 1, MI produced greater levels of covert excitation at the dominant biceps in comparison to control imagery (CI). In addition, covert excitation correlated significantly with imagery ability and imagery vividness. This excitation, however, did not predict motor task acquisition or retention. Experiment 2 attempted to manipulate pre-imagery relaxation states by giving 104 novice dart performers a relaxation task or a distraction task before imagery sessions. MI resulted in improved task retention and resulted in significantly greater covert muscle excitation at the frontalis in comparison to CI. The relaxation condition, however, did not yield greater levels of muscular relaxation in comparison to the distraction condition, and did not yield greater imagery vividness or motor performance. Finally, covert muscle excitation did not predict motor acquisition or retention error. Results suggest that covert excitation is a byproduct of the central generation of the image that does not relate meaningfully to motor skill acquisition or retention gains.

Evaluation of the Burkard Cyclonic Spore Sampler for Collection Efficiency of Ascospores.

The commercially available Burkard cyclonic sampler takes in air volumetrically, creates a vortex in an aluminum cylinder, and deposits particulates in an Eppendorf vial. Retention within the cylinder was determined for ascospores released by cultures of Sordaria fimicola and Gibberella zeae. Manufacturer's recommended amperage level and reduced power were tested, and a surfactant was applied to the cylinder wall. Under recommended power, an average of 78% of the S. fimicola ascospores were collected in the vial, while 22% lodged inside the cylinder. Conversely, only 25% of the G. zeae ascospores were collected in the vial, while 75% remained lodged inside the cylinder. Application of a surfactant to reduce the adherence of ascospores on the cylinder wall, instead resulted in 83% of the S. fimicola ascospores and 99.7% of the G. zeae ascospores deposited on the cylinder wall. When the power supply was decreased from 200 mA to 140 mA, the ratio of ascospores of G. zeae retained by the sampler remained nearly the same, indicating that the retention error was not a function of airflow rate within the tested power range. However, the total number of ascospores collected was significantly less under reduced power. A 90-A/h (12 V) battery supplied greater than 150 mA when connected to the Burkard for 4 days at temperatures between 22 and 28°C and could maintain current above 190 mA for 7 days with a 21-W solar panel. A 21-W solar panel charging a 90-A/h battery should maintain the amperage needed for the Burkard to maintain proper flow rate in most environments. The aluminum cylinder should be rinsed out thoroughly when collecting samples of fungal ascospores or any other particulates with the propensity to adhere to the cylinder wall.

Acquisition and Retention of Motor Skills as a Function of Age and Aerobic Fitness

Evidence suggests that cognitive ability declines with advancing age but that aerobic fitness can serve to minimize or even negate these declines. The purpose of this study was to examine the relationship between age, fitness, and retention. Twenty younger (M=24.2 years) and 18 older adults (M=66.6 years) practiced on the mirror star trace until they achieved a criterion. VO2max was measured. The number of trials required to reach criterion was predicted by VO2max, p &lt; .001. and age, p &lt; .02. Retention distance was also predicted by VO2max, p &lt; .001, and age, p &lt; .001. Analysis of relative alpha change at P3 and F4 indicated that a relative increase in left-hemisphere alpha and a relative decrease in right-hemisphere alpha were associated with retention errors. Thus, older and less aerobically fit adults required more trials to reach criterion and performed less well at retention, and changes in brain activity were associated with retention errors.