Abstract
NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.
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