Field Programmable Gate Array Resources Research Articles

FPGA‐based system for heart rate monitoring

The continuous monitoring of cardiac patients requires an ambulatory system that can automatically detect heart diseases. This study presents a new field programmable gate array (FPGA)-based hardware implementation of the QRS complex detection. The proposed detection system is mainly based on the Pan and Tompkins algorithm, but applying a new, simple, and efficient technique in the detection stage. The new method is based on the centred derivative and the intermediate value theorem, to locate the QRS peaks. The proposed architecture has been implemented on FPGA using the Xilinx System Generator for digital signal processor and the Nexys-4 FPGA evaluation kit. To evaluate the effectiveness of the proposed system, a comparative study has been performed between the resulting performances and those obtained with existing QRS detection systems, in terms of reliability, execution time, and FPGA resources estimation. The proposed architecture has been validated using the 48 half-hours of records obtained from the Massachusetts Institute of Technology - Beth Israel Hospital (MIT-BIH) arrhythmia database. It has also been validated in real time via the analogue discovery device.

FPGA-Based Sub-Microsecond-Level Real-Time Simulation for Microgrids With a Network-Decoupled Algorithm

The real-time simulation based on the field programmable gate array (FPGA) is receiving more and more attention. However, up to now, the simulation scale for the power electronic system is not so satisfactory due to the real-time requirement and the FPGA resource limitation. This paper proposes a sub-microsecond level real-time simulation method for microgrids. The power converters are modeled with fixed-admittance models and simulated with a compact electromagnetic transients program (EMTP) algorithm. In the meanwhile, the distribution lines/cables are modeled with π-circuit models and simulated with a distributed circuit solution method, called the latency insertion method (LIM). As a result, the distribution generation (DG) systems are decoupled with each other and can be simulated in parallel. The case study shows that the proposed simulation method consumes much fewer FPGA resources compared with the traditional one. Besides, the time step can be much smaller and doesn't need to increase with the simulation scale. With these advantages, the real-time simulation of a microgrid consisting of three three-phase converters, three boost circuits and 21 three-phase lines can be achieved on the Xilinx Kintex-7 410T FPGA with a minmum time-step of 380 ns.

An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA

We present a fast global and locally adaptive tone mapping algorithm and its field-programmable gate array (FPGA) implementation. The specially designed tone mapping function, which is based on local histogram equalization, controls global, and local characteristics individually. In contrast to other tonemap operators, our algorithm manages light/dark halos separately and by using local tonemap function alone, it can effectively suppress noise. We validated the effectiveness of our algorithms using subjective and objective assessment. Using an average of the bins, we achieve fast smoothed local histogram estimation with fewer bins while maintaining high accuracy. Our new implementation method requires minimal data access and reduced memory as it operates with a downscaled frame size of 240 × 135 pixels. Relative local area size is 248 × 248 @Full-HD resolution (1920 × 1080). For low-latency pixel output, the system performs the tone mapping using pixel information from the previous frame. When we implemented the system on FPGA (TB-7K-325TIMG and Xilinx Kintex-7), we achieved lightweight hardware as the total usage rate is about 25% of the available FPGA resource. Using an online 1080p video we demonstrate, a real-time video processing using our hardware tone mapping system.

PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration

Modern field-programmable gate arrays (FPGAs) provide a vast amount of logic resources that can be used to implement complex systems while providing the flexibility to modify the design once deployed. This makes them attractive for software-defined networks (SDNs) applications, and, in fact, most vendors provide the building blocks needed for those applications, which include basic packet classification functions such as exact match, longest prefix match, and match with wildcards. Those are needed for different functions such as routing, security filtering, monitoring or quality of service. The match with wildcards can be done using ternary content addressable memories (TCAMs). TCAMs can be implemented as independent standalone devices or as Internet Protocol (IP) blocks that are used inside networking application-specific integrated circuits (ASICs) such as switching ICs. In both cases, the cells of a TCAM are more complex than that of a normal memory and also than that of a binary content addressable memory (CAMs). This is due to the more complex matching that they need to implement. As FPGAs are used in many different applications, it does not make sense to include TCAM blocks inside them as they would be used only in a small fraction of the systems. Therefore, TCAMs are emulated using the logic resources available inside the FPGA. In recent years, a number of schemes to emulate TCAMs on FPGAs have been proposed, some of them based on the use of the logic resources and others on the use of the embedded memory blocks available on the FPGA. In this brief, a technique to efficiently emulate TCAMs on Xilinx FPGAs is presented. The proposed scheme is based on the use of lookup tables (LUTs) and partial reconfiguration to achieve a more effective use of the FPGA resources while supporting the addition and removal of rules. The proposed scheme has been compared to existing implementations and the results show that it can achieve significant savings in resource usage. In addition, it enables the use of all the LUTs in the device for TCAM implementation, something that is not supported by existing approaches that use LUTRAMs.

RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA

In this paper, we identify the general requirements for network-on-chips (NoCs) and the general characteristics of field-programmable gate arrays (FPGAs) from leading producers. Based on the analysis provided, an FPGA-oriented NoC called RingNet is proposed. As a distinctive feature, RingNet uses communication through a centrally placed memory that aims at preventing network congestions and limiting the network buffer requirements. Optimal utilization of FPGA resources is one of the goals of RingNet development. Especially buffers are implemented in distributed RAM available in FPGAs, and the virtual cut-through is used as an efficient switching technique for FPGA. Simulations prove guaranteed throughput, predictable latency, and fair network access provided by RingNet. Synthesis results for sample FPGAs from Xilinx, Intel, and Lattice prove the universality of RingNet. The provided analysis of NoC implementations leads to the conclusion that RingNet needs fewer resources and supports higher clock frequencies than the widely used AXI4 architecture.

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor (BAM) system, based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser. The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array (FPGA), mezzanine card (FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter (ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC, a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA

Deep learning is the amazing technology which has promoted the development of artificial intelligence and achieved many amazing successes in intelligent fields. Convolution-based layers (CLs), fully connected layers (FLs) and recurrent layers (RLs) are three types of layers in classic neural networks. Most intelligent tasks are implemented by the hybrid neural networks (hybrid-NNs), which are commonly composed of different layer-blocks (LBs) of CLs, FLs, and RLs. Because the CLs require the most computation in hybrid-NNs, many field-programmable gate array (FPGA)-based accelerators focus on CLs acceleration and have demonstrated great performance. However, the CLs accelerators lead to an underutilization of FPGA resources in the acceleration of the whole hybrid-NN. To fully exploit the logic resources and the memory bandwidth in the acceleration of CLs/FLs/RLs, we propose an FPGA resource efficient mapping mechanism for hybrid-NNs. The mechanism first improves the utilization of DSPs by integrating multiple small bit-width operations on one DSP. Then the LB-level spatial mapping is used to exploit the complementary features between different neural networks in the hybrid-NN. We evaluate the mapping mechanism by implementing four hybrid-NNs on Xilinx Virtex7 690T FPGA. The proposed mechanism achieves a peak performance of 1805.8 giga operations per second (GOPs). With the analysis on resource utilization and throughput, the proposed method exploits more computing power in FPGA and achieves up to $4.13 \times$ higher throughput than the state-of-the-art acceleration.

An Integrated on-Silicon Verification Method for FPGA Overlays

Field Programmable Gate Arrays (FPGAs) gain popularity as higher-level tools evolve to deliver the benefits of re-programmable silicon to engineers and scientists at all levels of expertise. In order to use FPGAs efficiently, new CAD tools and modern architectures are needed for the growing demands of heterogeneous computing paradigms. Overlay architectures have become a popular option to support a variety of high-performance computing applications implemented on heterogeneous computing platforms. However, most of these architectures cannot offer an efficient way to dynamically debug and repair them. In this paper, we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded with on-demand debug and self-healing capabilities. The proposed method automatically creates flexible techniques for in-circuit error detection and correction of generic Processing Elements and Virtual Channels. The debugging infrastructure is integrated in the design with tailor-made CAD tools, making feasible to rapidly debug and repair virtual architectures with minimal use of additional FPGA resources.

An Accelerator Architecture of Changeable-Dimension Matrix Computing Method for SVM

Matrix multiplication is a critical time-consuming processing step in many machine learning applications. Due to the diversity of practical applications, the matrix dimensions are generally not fixed. However, most matrix calculation methods, based on field programmable gate array (FPGA) currently use fixed matrix dimensions, which limit the flexibility of machine learning algorithms in a FPGA. The bottleneck lies in the limited FPGA resources. Therefore, this paper proposes an accelerator architecture for matrix computing method with changeable dimensions. Multi-matrix synchronous calculation concept allows matrix data to be processed continuously, which improves the parallel computing characteristics of FPGA and optimizes the computational efficiency. This paper tests matrix multiplication using support vector machine (SVM) algorithm to verify the performance of proposed architecture on the ZYNQ platform. The experimental results show that, compared to the software processing method, the proposed architecture increases the performance by 21.18 times with 9947 dimensions. The dimension is changeable with a maximum value of 2,097,151, without changing hardware design. This method is also applicable to matrix multiplication processing with other machine learning algorithms.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs. However, it is still difficult to achieve high performance multi-task acceleration in multi-FPGA systems due to the resource contention in limited hardware resources and reconfiguration overhead. In this paper, we propose a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. At the first scheduling stage, we select an appropriate computing unit for each task considering the subtask similarity and resource requirement similarity to reduce the possibility of reconfiguration and resource contention. At the second scheduling stage, we coordinate the subtask scheduling and placement to make full use of the hardware resources of FPGAs and improve the acceleration performance. Experiments show that our two-stage scheduling approach significantly reduces the tasks makespan and improves the utilization of resources compared with other traditional methods.

Edge computing for space applications: Field programmable gate array-based implementation of multiscale probability distribution functions.

Data processing is a challenging problem in space applications. The limited bandwidth available for communication between satellites and the ground and the increasing resolution of scientific instruments make it virtually impossible to transfer all the data recorded on board. Although various mitigation strategies were developed, large amounts of on-board data are still lost. This paper presents a Field Programmable Gate Array (FPGA)-based architecture which is able to perform on-board nonlinear analysis of data and compute probability distribution functions of fluctuations. We propose two implementations for our solution, which can be used for space applications and also other computational contexts. On a spacecraft, the logic resources of the FPGA will typically be shared by several designs running various digital signal processing algorithms. That is why each algorithm should be designed in variants, optimized for different criteria, so that the entire group of algorithms makes an efficient usage of the FPGA resources. The proposed solution focuses on two major optimization criteria, area and speed, such that the FPGA resources are efficiently used. Also, the power consumption is at least two orders of magnitude less in comparison with classical software implementations. The solution was tested with both synthetic and real data and shows excellent results paving the way towards an application that can be ported on a space-grade FPGA.

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

Field Programmable Gate Array (FPGA) technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long design and debug cycles. To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required on modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for small combinational and sequential circuits with a single output; such circuits are typical of common trigger functions. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40s instead of recompiling the circuit during debug iterations, increasing debug productivity.

The role of sub-interpolation for Delay-Line Time-to-Digital Converters in FPGA devices

Most of the Time-to-Digital Converters (TDCs) implemented in Field Programmable Gate Array (FPGA) devices are based on Tapped Delay Lines (TDLs). This solution makes mandatory the implementation of sub-interpolation procedures in the processing flow in order to mitigate effects of the different characteristics of the FPGA resources used.Specifically, we focus issues of the sub-interpolation topic also still outstanding and realize the experimental comparison of the state-of-art techniques, providing design rules for their optimal implementation.According to the host electronic device, the paper reveals the design rules to get the best performance, by using known sub-interpolation techniques but introducing criteria of choice and design procedures never presented in literature. These are fundamental for the most proper and useful application of sub-interpolation techniques in designing high-performance TDCs.

Hardware in the Loop Real-time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.

Real-Time DSP-Enabled Digital Subcarrier Cross-Connect Based on Resampling Filters

A real-time digital signal processing (DSP)- enabled digital subcarrier cross-connect (DSXC) with resampling filters for channel frequency translation is demonstrated in this paper. This circuit-based DSXC supports flexible and fine data-rate subcarrier channel granularities, offering a low-latency data plane, transparency to modulation formats, and the capability of compensating for transmission impairments in the digital domain. The presented 8 × 8 DSXC demonstrator makes use of a Virtex-7 field programmable gate array (FPGA) platform, which supports any-to-any switching of eight subcarrier channels with mixed modulation formats and data rates. Digital resampling filters enable frequency translation of subcarrier channels at the cross-connect with much reduced processing requirements for the FPGA resources in comparison to the traditional technique based on in-phase/quadrature mixing and filtering.

High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs

Reliability of Integrated Circuits (ICs) is nowadays a major concern for sub-micron technologies especially when they are adopted in mission critical applications. This paper presents a methodology for accurate characterization of radiation-induced Single Event Transients (SETs) effects in SRAM-based Field Programmable Gate Arrays (FPGAs). A technique based on internal electrical pulse injection is proposed for emulating SET within logic resources of SRAM-based FPGAs. Experimental results provide detailed characterization of basic logic gates.

CPU-FPGA based real-time simulation of fuel cell electric vehicle

Proton exchange membrane fuel cell (PEMFC) has been considered as one of the promising renewable power technologies for the vehicular application. This paper proposes a fuel cell electric vehicle (FCEV) power system model that can be implemented in the hardware-in-the-loop (HIL) emulation for real-time execution on field-programmable gate arrays (FPGAs). The FCEV model comprises three parts: a PEMFC, a Z-source inverter and a squirrel cage motor. To achieve an accurate and efficient FPGA resources’ utilization, the PEMFC model is implemented by CPU whereas the models of the DC-AC inverter and the electrical motor are built in FPGA. For the validation of the proposed power system, the real-time simulation tests are conducted with a high accuracy. The developed hybrid system model can reach a simulation time step of 100 ns for FPGA and 500 μs for CPU under the co-simulation mode. Moreover, the simulation under various system operating conditions indicates that the high performance can be reached by the hybrid system computed in real-time. The proposed real-time model can be used to design the on-line diagnostic and model predictive control method, which can help to test the FCEV before the commercial applications.