Resistive Random Access Memory Cells Research Articles

Theoretico-experimental analysis of bistability in the oscillatory response of a TaOx ReRAM to pulse train stimuli

Fading memory is the capability of a physical system to approach a unique asymptotic behaviour, irrespective of the initial conditions, when stimulated by an input from a certain class. Standard stimuli from the AC periodic class typically induce fading memory effects in non-volatile memristors, as uncovered for the first time back in 2016. Very recently, a deep investigation of resistance switching phenomena in a TaOx resistive random access memory cell revealed the capability of the nano-device to exhibit one of two possible oscillatory behaviours, depending upon the initial condition, when subject to a particular periodic excitation. This interesting finding was, however, left unexplained. Bistability is the simplest form of local fading memory. In a system, endowed with local fading memory under a given stimulus, the initial condition does not affect the long-term behaviour of the state as long as it is drawn from the basin of attraction of either of the distinct coexisting state-space attractors (two limit cycles for the periodically forced memristor acting as a bistable oscillator). Here, the history of the system, encoded in the initial condition, is, thus, erasable only locally through ad hoc stimulation. Motivated by the discovery of local history erase effects in our resistive random access memory cell, this study applies a powerful system-theoretic tool, enabling the analysis of the response of first-order systems to square pulse train-based periodic stimuli, known as the time-average state dynamic route, to an accurate physics-based mathematical model, earlier fitted to the nano-device, to determine a strategy for specifying the parameters of an excitation signal, consisting of the sequence of two square pulses of opposite polarity per period so as to induce various forms of monostability or multistability in the non-volatile memristor. In particular, as an absolute novelty in the literature, experimental measurements validate the theoretical prediction on the capability of the device to operate as one of two distinct oscillators, depending upon the initial condition, under a specific pulse train excitation signal. The coexistence of multiple oscillatory operating modes in the periodically forced resistive random access memory cell, an example par excellence of their unique non-linear dynamics, may inspire the development and circuit implementation of novel sensing and mem-computing paradigms.

Compensation architecture design utilizing residual resource to mitigate impacts of nonidealities in RRAM-based computing-in-memory chips

Resistive random access memory (RRAM) is a promising technology for energy-efficient in-memory computing. However, due to technology limits, RRAM device faces a series of reliability issues. Deep neural network (DNN) computing based on RRAM suffers from accuracy degradation. On the one hand, offline DNN training solutions are difficult to fully consider and simulate all nonidealities. Worse still, new error or nonideality may come up with the usage of RRAM, which further deteriorates the effectiveness of offline training. On the other hand, online training poses great challenges on programming overhead and device lifetime. The iterative write-verify technique to program multi-bit RRAM cells prolongs write latency more than 10× longer than read latency. To overcome these issues, we propose a compensation architecture and training designs to mitigate the realistic accuracy loss in RRAM chips with negligible hardware resource for RRAM-based DNN computing. Firstly, we add trainable compensation channels in crossbars utilizing the residual resource after original weight mapping. Secondly, an offline training procedure with computing output from hardware is triggered to settle down appropriate weight value in compensation channels. Experimental results demonstrate that the proposed design can guarantee ≤ 0.8% loss of accuracy in DNN even when nonidealities reduce the original accuracy down to ≤73%.

Modeling of Self-Aligned Selector Based on Ultra-Thin Metal Oxide for Resistive Random-Access Memory (RRAM) Crossbar Arrays.

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array.

A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

An analytical approach to engineer multistability in the oscillatory response of a pulse-driven ReRAM

A nonlinear system, exhibiting a unique asymptotic behaviour, while being continuously subject to a stimulus from a certain class, is said to suffer from fading memory. This interesting phenomenon was first uncovered in a non-volatile tantalum oxide-based memristor from Hewlett Packard Labs back in 2016 out of a deep numerical investigation of a predictive mathematical description, known as the Strachan model, later corroborated by experimental validation. It was then found out that fading memory is ubiquitous in non-volatile resistance switching memories. A nonlinear system may however also exhibit a local form of fading memory, in case, under an excitation from a given family, it may approach one of a number of distinct attractors, depending upon the initial condition. A recent bifurcation study of the Strachan model revealed how, under specific train stimuli, composed of two square pulses of opposite polarity per cycle, the simplest form of local fading memory affects the transient dynamics of the aforementioned Resistive Random Access Memory cell, which, would asymptotically act as a bistable oscillator. In this manuscript we propose an analytical methodology, based on the application of analysis tools from Nonlinear System Theory to the Strachan model, to craft the properties of a generalised pulse train stimulus in such a way to induce the emergence of complex local fading memory effects in the nano-device, which would consequently display an interesting tuneable multistable oscillatory response, around desired resistance states. The last part of the manuscript discusses a case study, shedding light on a potential application of the local history erase effects, induced in the device via pulse train stimulation, for compensating the unwanted yet unavoidable drifts in its resistance state under power off conditions.

Effect of heat treatment on resistive switching memory characteristics of NiO nanodots of tens of nanometers shattered by AFM tips

The characteristics of resistive random access memory (RRAM) at the nanometer scale are increasingly important for RRAM cells with further miniaturization. We report the RRAM characteristics of NiO nanodots in the order of tens of nanometers. NiO nanodots of approximately 70 nm were created on a single-crystal Nb-doped SrTiO3 (Nb:STO) substrate by dip-pen nanolithography. For comparison, a NiO thin film was also deposited on the Nb:STO substrate by spin coating. To reduce the size of NiO nanodots, they were shattered by an atomic force microscope tip, obtaining nanodots of approximately 10 nm. Using a conductive atomic force microscope, we characterized the current according to the applied electric field of the NiO nanodots on the Nb:STO substrate with a capacitor configured of Pt/NiO/Nb:STO substrate. When compared with the NiO thin film, the forming voltage of the NiO nanodots decreased. In addition, the shattered NiO nanodots exhibited unipolar switching characteristics, and the forming and set/reset voltages decreased with the reduction in nanodot size. Furthermore, the NiO nanodots exhibited a substantially reduced forming and set/reset voltages after heat treatment in vacuum. We suggest that the oxygen-depleted layer formed on the surface of NiO nanodots by heat treatment plays a crucial role in the reduction of the forming and operation voltages.

Thickness-dependent resistive switching memory characteristics of NiO nanodisks fabricated by AAO nanotemplate

Forming and set/reset operating voltages are critical issues encountered with a decrease in resistive random-access memory (RRAM) sizes. This study investigated the thickness-dependent resistive switching properties of NiO nanodisks. The NiO RRAM nanodisks, with a diameter of 100 nm and varying thicknesses, were fabricated on Pt/Ta/SiO2/Si substrates using anodic aluminum oxide templates through the RF sputtering process. In the electroforming process, the forming voltage of the NiO nanodisk effectively reduced with a decrease in the thickness. The electric field enhancement in localized regions appeared to contribute to the reduction in the forming voltage. In addition, the set/reset operating voltage of the NiO nanodisk RRAM decreased with a decrease in the thickness. We conclude that the use of the C-AFM tip strengthened the local electric field in NiO nanodisk RRAM cells, leading to the reduction of the set/reset voltage with a decrease in the thickness.

Enhanced resistive switching of silver copper iodide thin films prepared by interfacial phase formation

Resistive random-access memory (ReRAM), an alternative to conventional charge storage memory, employs the switching of a resistive material between high-resistance and low-resistance states, which can be generated by the formation/dissolution of metal filaments bridging the two electrodes in the cell. Silver iodide (AgI) is a promising solid electrolyte for ReRAM cells, but its application is hindered by poor photostability and low electrical conductivity. Herein, a Cu-substituted β-AgI system, β′-Ag0.7Cu0.3I, was successfully prepared via sequential deposition of a Cu metal layer onto a AgI thin film by a galvanic reaction, which induced the spontaneous incorporation of Cu+ cations into the AgI lattice. Cu substitution at the Cu–AgI heterojunction interface is a novel way to modulate the chemical composition and improve the resistive switching properties of intrinsic polycrystalline AgI thin films. We compared the resistive switching properties of a ReRAM thin film devices based on β′-Ag0.7Cu0.3I with those based on pristine β-AgI. This device exhibited enhanced performance with high ON/OFF ratio (∼104) and low working voltage compared with the β-AgI-based device. These results strongly suggest that binary metal halide materials can serve as simple model systems for the efficient formation of metal filaments and have potential low-cost, low-power memory applications.

Mapping and statistical analysis of filaments locations in amorphous HfO2 ReRAM cells

Two optical inspection techniques, Photon Emission Microscopy (PEM) and Optical Beam Induced Resistance Change (OBIRCH) laser stimulation, are used to study the forming and to map the locations of filaments in amorphous HfO2 Resistive Random-Access Memory (ReRAM) cells. The low voltage sensitivity of OBIRCH is used to investigate filament pre-forming while the high frame rate of a Silicon Intensified Charge-Coupled Device (SI-CCD) is used to dynamically study the filament after the initial forming. A Spatial Clustering Model (SCM) is developed to explain the non-Poisson spatial distribution of individual filaments measured from multiple cells of the same size.

Highly Reliable and Secure PUF Using Resistive Memory Integrated Into a 28 nm CMOS Process

Owing to the increased demand for secure communication channels and authentication steps, physical unclonable functions (PUFs) are increasingly important for hardware security. In this article, we report a novel PUF architecture and generation scheme that utilizes the inherent program-time variation of resistive random access memory (ReRAM) cells as an entropy source. ReRAM cells are integrated into a standard 28 nm CMOS manufacturing process, and also show robust non-volatile memory operation. We generated a PUF data set larger than 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\text{8}}$</tex-math> </inline-formula> bits and verified its randomness using a standard NIST test suite. Further verifications such as inter-and intra-hamming distance, 150 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C data retention of PUF bits, and spatial co-relation tests confirm the high reliability of the generated PUF keys.

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.

Synaptic plasticity and non-volatile memory characteristics in TiN-nanocrystal-embedded 3D vertical memristor-based synapses for neuromorphic systems.

Although vertical configurations for high-density storage require challenging process steps, such as etching high aspect ratios and atomic layer deposition (ALD), they are more affordable with a relatively simple lithography process and have been employed in many studies. Herein, the potential of memristors with CMOS-compatible 3D vertical stacked structures of Pt/Ti/HfOx/TiN-NCs/HfOx/TiN is examined for use in neuromorphic systems. The electrical characteristics (including I-V properties, retention, and endurance) were investigated for both planar single cells and vertical resistive random-access memory (VRRAM) cells at each layer, demonstrating their outstanding non-volatile memory capabilities. In addition, various synaptic functions (including potentiation and depression) under different pulse schemes, excitatory postsynaptic current (EPSC), and spike-timing-dependent plasticity (STDP) were investigated. In pattern recognition simulations, an improved recognition rate was achieved by the linearly changing conductance, which was enhanced by the incremental pulse scheme. The achieved results demonstrated the feasibility of employing VRRAM with TiN nanocrystals in neuromorphic systems that resemble the human brain.

SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator

Resistive random-access-memory (ReRAM) crossbar is a promising technique for deep neural network (DNN) accelerators, thanks to its in-memory and in-situ analog computing abilities for vector–matrix multiplication-and-accumulations (VMMs). However, it is challenging for crossbar architecture to exploit the sparsity in DNNs. It is inevitably complex and costly to exploit fine-grained sparsity due to the limitation of the tightly coupled crossbar structure. As a countermeasure, we develop a novel ReRAM-based DNN accelerator, named sparse-multiplication-engine (SME), based on a hardware and software co-design framework. First, we orchestrate the bit-sparse pattern to increase the density of bit-sparsity based on existing quantization methods. Such quantized weights can be nicely generated using the alternating direction method of multipliers (ADMM) optimization during the DNN fine-tuning, which can exactly enforce bit patterns in weights. Second, we propose a novel weight mapping mechanism to slice the bits of the weight across crossbars and splice the activation results in peripheral circuits. This mechanism can decouple the tightly coupled crossbar structure and cumulate the sparsity in the crossbar. Finally, a superior squeeze-out scheme empties the crossbars mapped with highly sparse nonzeros from the previous two steps. We design the SME architecture and discuss its use for other quantization methods and different ReRAM cell technologies. We further propose a workload grouping algorithm and a pipeline to achieve workload balance among crossbar-rows that concurrently execute multiply–accumulate operations to optimize the system latency. Putting all together, with the optimized model, compared with prior state-of-the-art designs, the SME shrinks the use of crossbars up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.7\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> using ResNet-50 and MobileNet-v2, respectively, and achieve average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.1\times $ </tex-math></inline-formula> speed up with no or little accuracy loss on ImageNet.

Formation of Remote Quantum Point Contact Inside Dielectric Medium of an AlO x /SiO x ReRAM

Remote quantum point contact (QPC) far from the metal electrodes was observed in forming free aluminum oxide (AlOx)/silicon oxide (SiOx) resistive random access memory (ReRAM) cell, which was resolved at low bias. QPC behavior of the cell was attributed to confined oxygen vacancies across uncorrelated narrow grain boundaries of intermediate O3 treated thin AlOx layer of the stack, which was designed to restrict vacancy channeling between the two immediate reservoirs; i.e., from beneath SiOx to the top as-deposited AlOx layer. From time dependent dielectric breakdown (TDDB) characteristics of the cell while assessed under low stress biases, we found one to one correspondence between TDDB and its bias dependent QPC. Furthermore, we found that, under steady state and especially at low biases progressive breakdown (PBD) of the dielectric exhibited two-level random telegraph noise (RTN) like conductance fluctuations, which occurred in the magnitude of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{{0}}$ </tex-math></inline-formula> or in its multiples depending on applied bias to the cell, that demonstrated a correlation between electron trapping and maximum QPC instability during filament growth. Low voltage QPC-based switching under dc bias sweep, its correlation with TDDB and RTN under the steady state thus provided us a framework to analyze the evolution of QPC well before reaching the SET state in an AlOx/SiOx cell, which is different from the usual QPC evolution as found near contact regions in a conventional SiOx cell without accompanying engineered AlOx barrier.

Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

Computing‐in‐memory (CIM) is considered a feasible solution to the acceleration of multiply‐accumulate (MAC) operations at low power. The key to CIM is parallel MAC operations in the memory domain, and thus reductions in power consumption and memory‐access latency. Resistive random access memory (RRAM) can be a good candidate for the memory for CIM given its data nonvolatility, high data density, low‐latency read‐out, multilevel representation, and inherent current accumulation capability. Particularly, the last two attributes offer analog MAC operations in parallel in the memory domain. However, the fully analog MAC operation scheme causes significant power and area overheads for its peripheral circuits, particularly, analog‐to‐digital converters. To compensate for these downsides using digital processing, a method for sub‐array‐wise partial MAC operations over weight‐resistors that are optimally split to minimize power and area overheads for the peripheral circuits is proposed. The simulations performed highlight the optimal sub‐array of in size. That is, weight‐splitting such that a single w‐bit weight is represented by RRAM cells, i.e., 2‐bit for each cell. For 8‐bit weights, the figure of merit (FOM) for this optimal case reaches ≈28.3 FOM for the case of no weight‐splitting.

(Excellent Student Presentation Award) Confined Conducting Filaments in Resistive Random Access Memory By Al2O3 Nanodome-Shaped Arrays (NDSAs) Via Glancing-Angle Deposition

Resistive random access memory (RRAM) is vital to neuromorphic computing applications. However, filamentary RRAM cells are affected by transitions from abrupt switching to analog switching. In this study, we develop Al2O3 nanodome shaped arrays (NDSAs) by glancing angle deposition technology (GLAD) to geometrically confine the conducting filaments (CFs), for which conducting atomic force microscopy (C-AFM) was performed to analyze positions and dimensions of filaments. For the Pt/HfO2/75 % Al2O3 NDSAs/TiN device, the dimension of the CFs can be restricted to 10-12 nm, whereas for the Pt/HfO2/TiN device, the CFs were formed with the dimension of ~50 nm. The device first yielded multiple weak CFs that subsequently transformed into stronger and larger CFs when the coverage of Al2O3 NDSAs was reduced to 55 % while Pt/HfO2/75 % Al2O3 NDSAs/TiN device exhibited synaptic features with more linear potentiation and depression, demonstrating the analog switching. The controllable coverages of Al2O3 NDSAs render the geometric design more promising as a memristor for future applications in neuromorphic computing.

Fully printed ZnO-based valency-change memories for flexible and transparent applications

Printable and flexible memory devices have attracted a great deal of attention in several emerging technological applications for the development of flexible electronics, such as interconnections/wearables/smart devices for the internet of things (IoT). In this work, we report on the fabrication of flexible, transparent, and fully inkjet-printed resistive random access memory (ReRAM) cells using poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS)/ZnO/PEDOT:PSS structures. The electrical characteristics were studied, including the determination of space charge limited conduction (SCLC) as the dominant charge transport mechanism. In addition, the bending performance and the transparency of the devices was tested in order to confirm the reliable operation and reproducibility of the cells. The switching for the printed structures of PEDOT:PSS/ZnO/PEDOT:PSS was led through the formation and dissolution of a stable oxygen vacancy filament, as confirmed by conductive atomic force microscopy. While the conduction mechanism for the high resistance state (HRS) was attributed to the SCLC mechanism. The switching of the memory cells, their endurance and retention properties were analysed and indicated the stability of the HRS and low resistance state for more than 104 cycles and 105 s comparable to ZnO-based ReRAM produced by clean-room techniques. The study of the mechanical flexibility of the cells shows that up to 700 bending cycles can be reached without significantly changing the switching characteristics.

Reliability Risks Due to Faults Affecting Selectors of ReRAMs and Possible Solutions

Resistive Random Access Memories (ReRAMs) are considered amongst the most promising candidates to replace silicon-based memories in the near future, when huge amount of data have to be stored. However, ReRAMs suffer from reliability issues associated to faults affecting both their resistive elements and their selectors. While some solutions have been presented in literature to detect, or tolerate, faults affecting the resistive element, so far no solution has been yet proposed to detect, or tolerate, faults affecting the selector, albeit these faults have been proven to be likely and possibly compromising the reliability of ReRAMs. In this paper, we analyze the effects of the most likely faults (i.e., shorts and opens) possibly affecting the selectors of ReRAM cells on the operation of the crossbar memory array. We show that a selector failing as a short can give rise to numerous errors on the ReRAM crossbar array. As an example, for the case of a crossbar array of 128x128 cells, we show that a single selector failing as a short may cause up to 64 errors in memory cells sharing the same word line of the cell containing the faulty selector. Such a large number of errors exceeds the correction capability of ECCs usually adopted for ReRAM arrays. Therefore, new solutions enabling to tolerate the large number of errors caused by selector faults in crossbar arrays are needed, to enable the use of this kind of promising memories in a reliable way. We then propose a low-cost approach to detect short faults affecting selectors of ReRAMs and to identify the bitline containing the cell whose selector is faulty. Such a bitline can then be properly deactivated and replaced by a spare one, in order to guarantee the memory correct operation in the field.

(Invited) Two-Dimensional Amorphous Carbon Prepared from Solution Precursor As Novel Dielectrics for Nanoelectronics

Low-dimensional electronic materials such as carbon nanotubes, graphene, and transition-metal chalcogenides have drawn a lot of interest from the aspects of both fundamental studies and practical applications. Their atomic-scale thickness and unique electrical properties make them become promising candidates as the drop-in replacement of conventional bulk electronic materials in future electronic devices to enable better performance and enhanced functionality. Research on low-dimensional electronic materials so far has predominantly focused on crystalline semimetals and semiconductors. However, advanced electronic devices also require suitable low-dimensional insulators, which are ideally in the highly disordered amorphous form, similar as SiO2 for silicon, to avoid the nonuniformity and defects related with grain boundaries, in order to fulfill their potentials. Here we present a new strategy for the solution-based preparation of atomically thin amorphous carbon as a novel 2D insulator. Our unique process can precisely control the film thickness at atomic level and has excellent scalability toward wafer-scale deposition. The obtained 2D amorphous carbon monolayer exhibits mechanical robustness comparable to graphene and can be suspended as a free-standing membrane on transmission-electron-microscopy grid, allowing the structural characterization down to atomic resolution. The structure-property relationship for such amorphous materials at 2D limit was then established based on a combination of experiment and density-functional theory simulation. The unique physical properties of 2D amorphous carbon suggest it as a promising candidate to accompany crystalline low-dimensional semiconductors and semimetals in future nanoelectronic devices, and its performance advantages over conventional 3D metal oxides and polycrystalline 2D insulators were verified in experiment : Serving as the gate dielectric in graphene transistors, the absence of grain boundaries in 2D amorphous carbon allows us to aggressively reduce the gate-dielectric thickness down to merely three-atomic layers to enhance the capacitance coupling between the gate and the channel, while still maintaining a low leakage current density below 10-4 A/cm2, which is many orders of magnitude lower compared to the leakage current across the polycrystalline hexagonal boron nitride with the same thickness. Meanwhile, the perfectly clean van der Waals interface it forms with the graphene channel leads to the sharply reduction of the device hysteresis and thus average effective mobility twice as high as that of devices built with bulk SiO2 as gate dielectric. Serving as the switching medium in resistive random access memory cells, the atomic-level thinness of the 2D amorphous carbon enables low operating voltage below 0.4 V, fast switching time <20 ns, and low energy consumption per write operation below 20 fJ, together with excellent endurance (>104) and data retention (>10 years @ 85oC). Moreover, its atomic structural heterogeneity provides well defined ion-transport pathways as suggested in ab initio simulations, leading to the drastically improved device-to-device and cycle-to-cycle uniformity with the standard deviation of Set/Reset voltages below 50 mV in experiment, which is among the lowest values ever reported for memristors. The concurrent achievement of all these performance metrics has not been accomplished with memristors built on either bulk oxides or polycrystalline 2D materials.

Bit-Aware Fault-Tolerant Hybrid Retraining and Remapping Schemes for RRAM-Based Computing-in-Memory Systems

Non-volatile computing-in-memory (nvCIM) has become one of the most efficient methods to deal with increasingly complicated neural networks compared to the traditional von Neumann architecture. However, due to the immature fabrication issues, the yield of resistive random access memory (RRAM) cells is limited, which causes the Stuck-At-Faults (SAFs) and decrease of network classification accuracy. In this brief, the bit-aware fault-tolerant hybrid retraining and remapping schemes are proposed to restore the network classification accuracy caused by SAFs. The low weight bits are retrained with the fault mask and the high weight bits are remapped with column swap and zero correction methods. For those bits whose values are still wrong after remapping, the fault index is used to record and calibrate. Experimental results show that the classification accuracy of MNIST, CIFAR-10, and CIFAR-100 is restored from 12.54% to 98.13%, from 10.29% to 90.60%, and from 0.94% to 74.30% with only 10.3% energy consumption and 5.88% area overhead, respectively.