Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

Abstract

Computing‐in‐memory (CIM) is considered a feasible solution to the acceleration of multiply‐accumulate (MAC) operations at low power. The key to CIM is parallel MAC operations in the memory domain, and thus reductions in power consumption and memory‐access latency. Resistive random access memory (RRAM) can be a good candidate for the memory for CIM given its data nonvolatility, high data density, low‐latency read‐out, multilevel representation, and inherent current accumulation capability. Particularly, the last two attributes offer analog MAC operations in parallel in the memory domain. However, the fully analog MAC operation scheme causes significant power and area overheads for its peripheral circuits, particularly, analog‐to‐digital converters. To compensate for these downsides using digital processing, a method for sub‐array‐wise partial MAC operations over weight‐resistors that are optimally split to minimize power and area overheads for the peripheral circuits is proposed. The simulations performed highlight the optimal sub‐array of in size. That is, weight‐splitting such that a single w‐bit weight is represented by RRAM cells, i.e., 2‐bit for each cell. For 8‐bit weights, the figure of merit (FOM) for this optimal case reaches ≈28.3 FOM for the case of no weight‐splitting.