Reordering Algorithm Research Articles

Speckle visual cryptography for credential authentication

Based on the high random distribution characteristic of the natural speckle image, a new method of speckle visual cryptography, to the best of our knowledge, is designed by combining the natural speckle image with the secret key in visual cryptography. Specifically, we designed an authentication system for user credentials by combining speckle visual cryptography and the QR code. By using the speckle visual cryptography method, the image of the QR code carrying user authentication information is hidden in the speckle image, and the speckle image is printed on the paper credentials. Through a simulation and analog experiments, we verify the possibility of applying speckle visual cryptography to a user credentials authentication system, compare the improved grayscale reordering algorithm and grayscale reordering algorithm, and prove that the improved grayscale reordering algorithm has more advantages in this system by comparing the PSNR and SSIM. Finally, the y-interference ability and the uniqueness of the virtual secret key in the system are analyzed to prove that the secret key has high anti-interference ability and security.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

An Efficient and Robust ILU(k) Preconditioner for Steady-State Neutron Diffusion Problem Based on MOOSE

Jacobian-free Newton Krylov (JFNK) is an attractive method to solve nonlinear equations in the nuclear engineering community, and has been successfully applied to steady-state neutron diffusion k-eigenvalue problems and multi-physics coupling problems. Preconditioning technique plays an important role in the JFNK algorithm, significantly affecting its computational efficiency. The key point is how to automatically construct a high-quality preconditioning matrix that can improve the convergence rate and perform the preconditioning matrix factorization efficiently and robustly. A reordering-based ILU(k) preconditioner is proposed to achieve the above objectives. In detail, the finite difference technique combined with the coloring algorithm is utilized to automatically construct a preconditioning matrix with low computational cost. Furthermore, the reordering algorithm is employed for the ILU(k) to reduce the additional non-zero elements and pursue robust computational performance. A 2D LRA neutron steady-state benchmark problem is used to evaluate the performance of the proposed preconditioning technique, and a steady-state neutron diffusion k-eigenvalue problem with thermal-hydraulic feedback is also utilized as a supplement. The results show that coloring algorithms can automatically and efficiently construct the preconditioning matrix. The computational efficiency of the FDP with coloring could be about 60 times higher than that of the preconditioner without the coloring algorithm. The reordering-based ILU(k) preconditioner shows excellent robustness, avoiding the effect of the fill-in level k choice in incomplete LU factorization. Moreover, its performances under different fill-in levels are comparable to the optimal computational cost with natural ordering.

Diversity enforced Genetic Algorithm (GA) for Binary Decision Diagram (BDD) reordering

Binary Decision Diagrams (BDDs) have become the state-of-art data structures in numerous fields, wherein, small-sized BDDs are required to reduce the companion cost. Since BDD size is sensitive to the order of variables for the Boolean function in use, evolutionary algorithms have been extensively exploited to solve the BDD reordering problem which is provably an NP-hard problem. However, getting trapped in a local minima is more likely as the population gets homogeneous during the evolution of the algorithm. This paper compares various diversity measures correlated to BDDs and studies the impact of different crossover and mutations used in the Genetic Algorithm (GA) on those diversity measures. Thereafter, we propose an enhanced GA-based reordering algorithm for BDD, wherein, the chosen diversity measure is calculated per generation to steer the application of proper variation operators, in such a way that an acceptable level of equilibrium between exploration and exploitation is preserved. Finally, we utilize a new heuristic Cyclic Crossover (HCX) that further improves the performance of the proposed algorithm following the fitness value. Experimental results on public benchmarks show that our proposed algorithm outperforms other algorithms from the literature when switching between HCX and swap mutation operators is made following the measured diversity metric.

Deep Reinforcement Learning for Mapping Quantum Circuits to 2D Nearest‐Neighbor Architectures

AbstractRecently, quantum computing is considered as a promising future computing paradigm. However, when implementing quantum circuits on a quantum device, it is necessary to ensure that quantum circuits satisfy nearest‐neighbor architecture constraints. When performing nearest‐neighbor architecture mapping for quantum circuits, it is inevitable to introduce SWAP gates, which will increase the overhead and reduce the fidelity. Therefore, it is crucial to complete the mapping with the minimum SWAP. In this paper, a 2D nearest‐neighbor architecture mapping method for quantum circuits is proposed based on deep reinforcement learning. In the initial mapping, an isomorphic graph initial mapping search algorithm is designed to quickly find the isomorphic graph between quantum circuit and architecture constraint graph. For quantum circuits without isomorphic graph mapping, the reordering algorithm of qubit impact factors is designed to obtain the initial placement position of qubits. In the SWAP gate addition, a qubit local reordering algorithm based on dueling deep‐Q‐network is designed to reduce SWAP gates. Experiments on the benchmark set B131 and IBM Q20 Tokyo verify that the proposed method can add fewer SWAP gates. Compared with the state‐of‐the‐art method, the average running time is accelerated by 63.1%, and the average SWAP gates added are reduced by 24.7%.

Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression

Sparse matrix-vector multiplication (SpMV) on FPGAs has gained much attention. The performance of SpMV is mainly determined by the number of multiplications between non-zero matrix elements and the corresponding vector values per cycle. On the one side, the off-chip memory bandwidth limits the number of non-zero matrix elements transferred from the off-chip DDR to the FPGA chip per cycle. On the other side, the irregular vector access pattern poses challenges to fetch the corresponding vector values. Besides, the read-after-write (RAW) dependency in the accumulation process shall be solved to enable a fully pipelined design. In this work, we propose an efficient FPGA-based sparse matrix-vector multiplication accelerator with data reuse-aware compression. The key observation is that repeated accesses to a vector value can be omitted by reusing the fetched data. Based on the observation, we propose a reordering algorithm to manually exploit the data reuse of fetched vector values. Further, we propose a novel compressed format called data reuse-aware compressed (DRC) to take full advantage of the data reuse and a fast format conversion algorithm to shorten the preprocessing time. Meanwhile, we propose an HLSfriendly accumulator to solve the RAW dependency. Finally, we implement and evaluate our proposed design on the Xilinx Zynq-UltraScale ZCU106 platform with a set of sparse matrices from the SuiteSparse matrix collection. Our proposed design achieves an average 1.18x performance speedup without the DRC format and an average 1.57x performance speedup with the DRC format w.r.t. the state-of-the-art work respectively.

Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS

We have developed a sparse matrix reordering algorithm with a novel 3D-SRAM-centric Polyomino accelerator that enables efficient processing of the reordered matrix for parameter compression. By reordering randomly pruned, irregularly structured sparse matrices into regularly structured matrices, both the compression ratio of the data and the efficiency of the hardware processing increase. The reordering algorithm can be implemented simply by attributing it to the widely known k-sum problem. We also developed a compression format for storing the reordered matrices and show that the reordered regular structure can reduce the amount of required memory by 63% compared with the conventional method. The proposed Polyomino accelerator can efficiently process reordered matrices by using a 3D stacked SRAM, which is an external memory with random accessibility and low latency. The measurement results using a test chip fabricated in a 180-nm CMOS process demonstrate that the proposed accelerator can achieve high area-efficiency and high energy-efficiency and scales well with the pruning rate.

A comparative analysis of matrix reordering algorithms regarding canonical data patterns

Matrix reordering is an Information Visualization topic that aims to study how to reveal information hidden within matrix-based visualizations, through appropriate reordering of its rows and columns. Considering the plethora of algorithms currently available to perform this task, and the set of matrix patterns presented in the visualization literature, we noted a lack of a comprehensive comparative analysis related to a subset of these patterns, known as canonical data patterns. Thus, this work aimed to perform a broad comparison of 37 state-of-the-art reordering algorithms by measuring the efficiency (execution time) and effectiveness (which combines objective functions as Moore Neighborhood, Minimal Span Loss Function and Circular Correlation, and a qualitative approach by visually assessing the output matrices) of the algorithms. We used as input a large synthetic matrix data set with different canonical data patterns. As a result, it was possible to indicate the most appropriate reordering algorithms for each pattern considered.

2D Wavelet Tree Ordering Based Localized Total Variation Model for Efficient Image Restoration

The degraded image during the process of image analysis needs more number of iterations to restore it. These iterations take long waiting time and slow scanning, resulting in inefficient image restoration. A few numbers of measurements are enough to recuperate an image with good condition. Due to tree sparsity, a 2D wavelet tree reduces the number of coefficients and iterations to restore the degraded image. All the wavelet coefficients are extracted with overlaps as low and high sub-band space and ordered them such that they are decomposed in the tree ordering structured path. Some articles have addressed the problems with tree sparsity and total variation (TV), but few authors endorsed the benefits of tree sparsity. In this paper, a spatial variation regularization algorithm based on tree order is implemented to change the window size and variation estimators to reduce the loss of image information and to solve the problem of image smoothing operation. The acceptance rate of the tree-structured path relies on local variation estimators to regularize the performance parameters and update them to restore the image. For this, the Localized Total Variation (LTV) method is proposed and implemented on a 2D wavelet tree ordering structured path based on the proposed image smooth adjustment scheme. In the end, a reliable reordering algorithm proposed to reorder the set of pixels and to increase the reliability of the restored image. Simulation results clearly show that the proposed method improved the performance compared to existing methods of image restoration.

An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks

Designing hardware accelerators for convolutional neural networks (CNNs) has recently attracted tremendous attention. Plenty of existing accelerators are built for dense CNNs or structured sparse CNNs. By contrast, unstructured sparse CNNs can achieve higher compression ratio with equivalent accuracy. However, their corresponding hardware implementations generally suffer from load imbalance and conflict access to on-chip buffers, which results in under utilization of processing elements (PEs). To tackle these issues, we propose a hardware/power-efficient and highly flexible architecture to support both unstructured and structured sparse CNNs with various configurations. Firstly, we propose an efficient weight reordering algorithm to preprocess compressed weights and balance the workload of PEs. Secondly, an adaptive on-chip dataflow, namely hybrid parallel (HP) dataflow, is introduced to promote weight reuse. Thirdly, the partial fusion scheme, which was first introduced in one of our prior works, is incorporated as the off-chip dataflow. Benefited from dataflow optimizations, the repetitive data exchanges between on-chip buffers and external memories are significantly reduced. We implement the design on the Intel Arria10 SX660 platform and evaluate with MobileNet-v2, ResNet-50, and ResNet-18 on ImageNet dataset. Compared to existing sparse accelerators on FPGAs, the proposed accelerator can achieve $1.35\sim 1.81\times $ improvement in power efficiency with the same sparsity. Compared to prior dense accelerators, this accelerator can achieve an improvement of $1.92\sim 5.84\times $ in DSP efficiency.

Methods for optimizing the delivery of goods to consumers by several vehicles

Freight transport is one of the most important sectors of the national economy. The increase in the efficiency of the logistics company is ensured by the accurate organization of supplies, as well as the timely delivery of goods to the points of the route. That is why there is a need to optimize the delivery of goods. A delivery task is a transport task of delivering oversized cargo from a distribution center to a multitude of recipients located in the area of operation of a transport company. It is a generalization of the well-known traveling salesman problem, from which it differs in the condition of the limited carrying capacity of the vehicle used and, as a consequence, the need to repeatedly return to the base to replenish the transported cargo. This article proposes to supplement the traditional formulation of the problem with the requirement to distribute customers among several simultaneously operating vehicles (TC) so that the maximum lead time is minimal. This takes into account not only the interests of the delivery contractor, but also the customers. The solution to the problem consists of two stages. On the first one, in some known way, rational ring routes for each vehicle are determined, minimizing the total mileage. Based on the results of the stage, the time for passing each route is calculated. At the second stage, the problem of reducing the maximum travel time of routes is solved by using several vehicles delivering at the same time. To do this, it is necessary to optimally distribute vehicles along individual routes. It is proposed to use the algorithm for solving the well-known problem "Packing items into containers" to solve this problem. This problem belongs to the class of NP-hard problems in the strong sense and does not have an exact solution algorithm for arbitrary input data. This paper proposes a complex solution method combining the well-known First fitted (FF) algorithm, the original First fitted with reordering (FFR) algorithm, and S. Martello's lower bounds and P. Thoth to control the optimality of the obtained solution. Test calculations have shown the effectiveness of this approach for a moderate dimension of the problem.

A fast Binary Decision Diagram (BDD)-based reversible logic optimization engine driven by recent meta-heuristic reordering algorithms

Reversible logic has recently gained a remarkable interest due to its information lossless property, which minimizes power dissipation in the circuit. Furthermore, with their natural reversibility, quantum computations can profit from the advances in reversible logic synthesis, as the latter can be easily applied to map practical logic designs to quantum architectures. Although numerous algorithms have been proposed to synthesize reversible circuits with low cost, the increasing demands for scalable synthesis techniques represent a serious barrier in the synthesis process. Furthermore, the enhanced reliability of the synthesized circuits comes at the cost of redundancy in the quantum architecture of the gates composing that circuit, which increases the overall manufacturing cost for fault-tolerant circuits. Binary Decision Diagram (BDD) based synthesis has demonstrated a great evidence in reversible logic synthesis, due to its scalability in synthesizing complex circuits within a reasonable time. However, the cost of the synthesized circuit is roughly correlated to its corresponding BDD size. In this paper, we propose a fast reversible circuit synthesis methodology driven by a BDD-reordering optimization engine implemented by recent meta-heuristic optimization algorithms. Experimental results show that Genetic Algorithm (GA) based reordering supported with Alternating Crossover (AX) and swap mutation outperforms others as it is the least destructive for low-cost BDDs during the optimization recipe.

An analysis of low power testing using K ‐means clustering with reordering approach

K-means clustering is a machine learning algorithm used to group the data based on the similarity between the data. Functional distances like squared Euclidean distance, city block, cosine, correlation and hamming are considered as a similarity parameter here. Test vectors are grouped based on the functional distance using the K-means algorithm. A simple reordering algorithm is proposed and is applied to each group of data before ‘X’ bit filing to minimize the test power. Experimental results on ISCAS 89 benchmark circuit shows that the proposed methods diminish the power effectively.

A kernel based reordering algorithm

We present in this short working paper a reordering algorithm, that we found quite handy while working in the context of Reproducing Kernel Hilbert Space (RKHS) theory. This algorithm, based on the linear assignment value problem, is used in a number of our research or industrial applications. It is integrated into our python library, named CodPy. CodPy stands for “Curse of dimensionality in Python” and is a Support Vector Machine (SVM), application oriented, Python library, providing tools for machine learning, statitistical learning and numerical simulations, consisting in a standard implementation of reproducing kernel Hilbert space (RKHS) methods.

Improving Compression Ratios for Code-Based Test Pattern Compressions through Column-Wise Reordering Algorithms

Chip testing is an effective way to reduce the number of defective or faulty chips that reach the market. However, as large-scale test patterns need to be transmitted into a circuit under test during testing, the transmission time dominates the test application time of the chip testing. Therefore, code-based compression methods are widely used in compressing test patterns because of their capability to reduce the transmission time and save storage space significantly. Current code-based compression methods cannot fully apply the inherent characteristics of test patterns yet. To address this problem, this study proposes two-stage test pattern preprocessing algorithms, thereby improving the efficiency of the code-based compression method. First, we propose a column-wise reordering for Hadamard matrix (CRHM) algorithm, which decomposes a test set consisting of test patterns into a primary component set (PCS) and a residual component set (RCS). The PCS inherits some 1s from the original test set (OTS), and other 1s belong to the RCS. As the number of 1s contained in the RCS is less than that in the OTS, the RCS can obtain a higher code-based compression ratio. The PCS can be generated by an on-chip generator, which does not consume transmission time. Second, we propose a novel column-wise reordering for the RCS (CRRCS) algorithm. The CRRCS solves the new location of each column of the RCS one by one in the list to decrease the entropy of the RCS. The entropy denotes the shortest length of the codeword required for the symbol to be encoded. The smaller entropy value refers to a higher compression ratio. For the sorted RCS, more high-frequency symbols can be replaced by shorter codewords. Experimental results based on seven code-based compression methods show that the proposed algorithms can increase the average compression ratio by a total of 19.91%, and the highest average compression ratio reaches 85.04% for ISCAS’89 benchmark circuits.

Natural speckle-based watermarking with random-like illuminated decoding.

We propose an optical watermarking method based on a natural speckle pattern. In the watermarking process, the watermark information is embedded into the natural speckle pattern. Then the random-like watermarked image is generated with the proposed grayscale reordering algorithm. During the extraction procedure, the watermarked image is projected to the natural speckle pattern as illumination. Subsequently, they are incoherently superimposed to extract the watermark information directly by human vision. Optical experiments and a hypothesis test are conducted to demonstrate the proposed method with high reliability, imperceptibility and robustness. The proposed method is the first watermarking method utilizing the natural diffuser as the core element in encoding and decoding.

Efficient Convergence for a Higher-Order Unstructured Finite Volume Solver for Compressible Flows

This Paper presents a three-dimensional higher-order-accurate finite volume algorithm for the solution of steady-state compressible flow problems. Higher-order accuracy is achieved by constructing a piecewise continuous representation of the average solution values using the -exact reconstruction scheme. The pseudo-transient continuation method is employed to reduce the solution of the discretized system of nonlinear equations into the solution of a series of linear systems, which are subsequently solved using the generalized minimal residual (GMRES) method. This Paper considers several preconditioning methods in conjunction with different matrix reordering algorithms and shows that the proposed preconditioner based on inner GMRES iterations can enhance the convergence speed and reduce the memory cost of the solver. Moreover, when starting from a lower-order solution as the initial condition, this Paper shows that ramping up the Courant–Friedrichs–Lewy (CFL) number accelerates the convergence rate. Finally, this Paper verifies the developed finite volume algorithm by solving a set of test problems, in which optimal solution convergence with mesh refinement is attained.

Reversible Logic Synthesis Using Binary Decision Diagrams With Exploiting Efficient Reordering Operators

With the continuous shrinkage of transistor sizes in very large scale integrated circuits, power consumption forms a serious concern to be tackled. With their ability to allow for zero energy dissipation, reversible circuits have been considered as promising solution to meetup with low power design requirements. Moreover, advances in their synthesis methodologies can be easily applied to quantum circuits due to the inherited reversibility of the latter. Although numerous algorithms have been proposed in the literature to synthesize reversible circuits and map them into their corresponding quantum circuits, the scalability and computational effort of such algorithms form a serious concern when synthesizing large size input functions. Binary Decision Diagram-based synthesis for reversible circuits has shown great evidence in realizing reversible circuits with low quantum cost through exploiting proper reduction rules for smaller graph size. However, the order of the variables in the decision diagram impacts its overall size, and thus, the cost of its corresponding reversible circuit. While several reordering algorithms have been proposed in this manner, their direct impact on the quantum cost has not been considered. In this article, a Binary Decision Diagram-based algorithm for reversible circuit synthesis is proposed to synthesize reversible circuits for a given Boolean function with low quantum cost through exploiting a linearized relationship between the decision diagram size and the corresponding quantum cost. Thereafter, different decision diagram reordering algorithms have been integrated with the proposed algorithm and compared in terms of their impact on the quantum cost. Experimental results show that Genetic Algorithm-based reordering for decision diagram, supported with, cycle crossover, inverse mutation, and tournament selection, results in the least quantum cost of the output circuit if compared with other algorithms due to its property in preserving the nodes of the decision diagram in their near-optimal locations during the optimiation recipe.

Temporal incoherence elimination for 2D color Doppler echocardiography via masking algorithm

Subject of Research. We introduce a novel method for resolving temporal incoherence in two-dimensional color Doppler echocardiography (2D CDE). Incoherence occurs when the temporal distance between frames is less than frame duration. This happens for frame reordering algorithms, which is a widespread processing method. Existing solution — temporal weighting — requires a lot of time for processing (more than 2 seconds per frame) and is not designed for blood flow data. Method. In the proposed method, the weights are calculated not per pixel, but per image subsector obtained by a specific precomputed mask,utilizing the mechanics of the acquisition process. Pixels with opposite blood flow directions are weighted separately with the further weights comparison. We evaluated the algorithm with 10 animal epicardial 2D CDE datasets of the right ventricle. Main Results. Measurements of differences in execution time and results (pixel intensities) with temporal weighting have shown the order of magnitude increase of processing speed from 0.40 frame/s to 4.63 frame/s. Pixel intensity changes inconsiderably: the average difference value is , maximum with intensity values lying within integer range of. Practical Relevance. The proposed algorithm can be embedded into reordering-based 2D CDE processing pipelines in order to obtain temporally correct results. In addition, the processing speed is close to real-time.

Evolving reordering algorithms using an ant colony hyperheuristic approach for accelerating the convergence of the ICCG method

This paper proposes a novel ant colony hyperheuristic approach for reordering the rows and columns of symmetric positive definite matrices. This ant colony hyperheuristic approach evolves heuristics for bandwidth reduction applied to instances arising from specific application areas with the objective of generating low-cost reordering algorithms. This paper evaluates the resulting reordering algorithm in each application area against state-of-the-art reordering algorithms with the purpose of reducing the running times of the zero-fill incomplete Cholesky-preconditioned conjugate gradient method. The results obtained on a wide-ranging set of standard benchmark matrices show that the proposed approach compares favorably with state-of-the-art reordering algorithms when applied to instances arising from computational fluid dynamics, structural, and thermal problems.