Ultra-thin Gate Oxide Reliability Research Articles

A Compact Model for Oxide Breakdown Failure Distribution in Ultrathin Oxides Showing Progressive Breakdown

The cumulative distribution of the failure time, which includes the time to first breakdown (BD) and the progressive current growth time, is the function of interest for reliability of ultrathin gate oxides. Depending on oxide area and stress conditions, oxide failure is determined by a single BD spot or by multiple competing spots. In this letter, we present an analytical compact model for the final failure distribution which is valid for any failure percentile and which is applicable to both the single and the multiple BD spot limits. This model is intended to be the core of a reliability assessment methodology either for the SiO2-based or high-k gate insulators of interest for the hp45 technology node and beyond.

The dynamic reliability of ultra-thin gate oxide and its breakdown characteristics

The experiment result shows that under unipolar voltage stress, electrons tunneling into ultra-thin gate oxide during on-time will recombine with the trapped holes, and neutral electron traps would be generated. These electron traps would assist electrons tunneling into gate oxide. It is proposed that the characteristic time τ for the charge to be trapped in SiO2 is longer than the on-time ton of unipolar stress. During the on-time few charges are trapped and during the off-time some trapped charges will be detrapped, thus very few neutral electron traps are generated. With the stress time increasing, the density of neutral electron traps would reach a critical value, and then the gate oxide would break down abruptly. The increase in unipolar breakdown time tBD is attributed to fewer charge trapping during the on-time and charge detrapping during the off-time.

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V FB < V G < 0 V and the second for V G < V FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of ∼0.036 decade/°C.

Growth of heavy ion-induced nanodots at the SiO2–Si interface: Correlation with ultrathin gate oxide reliability

Scaling-down the oxide thickness induces weakness influencing its intrinsic reliability. Even unbiased, swift heavy ions irradiated devices clearly show oxide alteration. Despite numerous studies on oxide reliability, some results are not yet well understood. In this paper, we focus on the structural degradation induced in thin silicon oxide films on silicon substrate after a 210MeV low fluence gold ion irradiation and on its effect on the reliability of MOS devices in radiation-harsh environments. We describe such degradation as a local silicon growth in the SiO2 layer, near the SiO2–Si interface. Experimental results can bring some emergent elements to explain earlier works in the field of oxide reliability. Based on the specific behavior of heavy ion-irradiated oxides, this paper aims to link together thermal spike model, heavy ion-induced nanodots and reliability of ultrathin gate oxides. We propose to evaluate the possible sensitivity of some high-k materials in radiation-harsh environments with respect to their thermal conductivity property.

Effect of oxidation temperature on the quality and reliability of ultrathin gate oxide

In this paper, we have studied the effect of oxidation temperatures on the quality and reliability of the ultrathin oxide. It has been observed that for the same oxide thickness, MOS capacitors exhibit a higher leakage current and lower breakdown voltage when the oxide is grown at a lower temperature. We have correlated this increase in leakage current to the effective electron tunnel mass parameter ( m*) and shown that with reduction in the oxidation temperature, the value of m* reduces, signifying the presence of more defects and an increase in defect-assisted tunneling. Also, voltage ramp tests have been carried out to study the time to breakdown ( t BD) and the shape factor ( β) of the Weibull distribution for these devices. It is found that lowering the oxidation temperature adversely affects both of these parameters.

Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability

The properties of the so-called time dependent dielectric breakdown (TDDB) of silicon dioxide-based gate dielectric for microelectronics technology have been investigated and reviewed. Experimental data covering a wide range of oxide thickness, stress voltage, temperature, and for the two bias polarities were gathered using structures with a wide range of gate oxide areas, and over very long stress times. Thickness dependence of oxide breakdown was shown to be in excellent agreement with statistical models founded in the percolation theory which explain the drastic reduction of the time-to-breakdown with decreasing oxide thickness. The voltage dependence of time-to-breakdown was found to follow a power-law behavior rather than an exponential law as commonly assumed. Our investigation on the inter-relationship between voltage and temperature dependencies of oxide breakdown reveals that a strong temperature activation with non-Arrhenius behavior is consistent with the power-law voltage dependence. The power-law voltage dependence in combination with strong temperature activation provides the most important reliability relief in compensation for the strong decrease of time-to-breakdown resulting from the reduction of the oxide thickness. Using the maximum energy of injected electrons at the anode interface as breakdown variable, we have resolved the polarity gap of time- and charge-to-breakdown ( T BD and Q BD), confirming that the fluency and the electron energy at anode interface are the fundamental quantities controlling oxide breakdown. Combining this large database with a recently proposed cell-based analytical version of the percolation model, we extract the defect generation efficiency responsible for breakdown. Following a review of different breakdown mechanisms and models, we discuss how the release of hydrogen through the coupling between vibrational and electronic degrees of freedom can explain the power-law dependence of defect generation efficiency. On the basis of these results, a unified and global picture of oxide breakdown is constructed and the resulting model is applied to project reliability limits. In this regard, it is concluded that SiO 2-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable for the 50 nm technology node.

Effects of plasma nitridation on ultra-thin gate oxide electrical and reliability characteristics

The gate leakage current and reliability concern become more serious due to the aggressive scaling-down of the gate oxide thickness. In this paper, the gate leakage current reduction and reliability optimization with an EOT 15A plasma nitrided gate oxide were explored. The plasma nitrided oxide fabricated by plasma nitridation process demonstrated good gate leakage reduction and high carrier mobility without sacrificing the reliability performance. The optimization of nitrogen profile and post nitridation annealing has been also discussed.

Improved quality and reliability of ultrathin (1.4–2.3 nm) gate oxides by radical-assisted oxidation utilizing a remote ultraviolet ozone source

A low-temperature and high-purity radical-assisted oxidation (RAO) process for the growth of ultrathin (1.4–2.3 nm) gate oxides was successfully developed utilizing a remote ultraviolet ozone source. The metal–oxide–semiconductor transistors with RAO gate oxides showed improved device characteristics and oxide reliability, in comparison with the devices with non-RAO or standard furnace oxides. The RAO process in this study was proven to be an effective technique to make the oxide network robust and dense, without an increase of growth temperature.

Substrate bias dependence of breakdown progression in ultrathin oxide pMOSFETs

Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is particularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.

Ultrathin gate oxide reliability: physical models, statistics, and characterization

The present understanding of wear-out and breakdown in ultrathin (t/sub ox/ < 5.0 nm) SiO/sub 2/ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed.

Ultra-thin gate oxide reliability projections

We describe the reliability projection methods currently used and show that 1.6 nm oxides are sufficiently reliable even if soft breakdown is considered the point of failure. We also explore the possibility of using oxides after soft breakdown.

Reliability of ultrathin nitrided oxides grown in low pressure N 2O ambient

The influence of N 2O oxynitridation and oxidation pressure on reliability of ultrathin gate oxides from 4 down to 2.5 nm thickness was investigated. A set of different oxidation parameters was applied during oxide growth which comprised oxidation pressure and N 2O partial pressure during rapid thermal oxidation. The reliability of the oxides was tested by constant voltage stress. Evaluation of the resulting times to soft breakdown ( t sbd) for different stress voltages allows to predict a supply (gate) voltage V 10 y, max providing an oxide lifetime of 10 years. For this extrapolation, t sbd was assumed to increase exponentially as stress voltage is reduced. The slope of the extrapolation is found to become steeper as oxides become thinner, which implies higher V 10 y, max and thus higher reliability for thinner oxides as under an assumption of a uniform slope for all thicknesses. Further, the results of this extrapolation demonstrate that oxidation in N 2O containing ambient can improve oxide reliability for ultrathin gate oxides.

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.

Reliability of Thin Gate Oxides Irradiated under X-Ray Lithography Conditions

The effect of X-ray lithography (XRL) process on the reliability of thin gate oxide has been investigated. A large increase in the low-field excess leakage current was observed on irradiated oxides, which was very similar to the electrical stress-induced leakage currents. However, it has been found that the long-term reliability of ultra-thin gate oxide is not affected by XRL process. The excess leakage current could be eliminated by thermal annealing at 400°C and above and no residual damages in the oxide were observed after the annealing.

A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs

This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.

Investigation of Reliability Degradation of Ultra-Thin Gate Oxides Irradiated under Electron-Beam Lithography Conditions

The effect of Electron-beam irradiation on the reliability of ultra-thin gate oxide has been studied under typical Electron-beam lithography conditions. A large increase of low-field excess leakage current was observed on irradiated oxides, which was found to be very similar to the electrical stress-induced leakage currents. An experimental relationship between the total Electron-beam dosage and the equivalent charge fluence, which induces the same amount of current degradation, has been established for different oxide thickness. This allows for easier prediction of radiation damage. It has also been found that Electron-beam irradiation generates much larger amount of oxide bulk traps but generates a comparable amount of interface states, compared to electrical stress. Quasi-breakdown characteristics show that Electron-beam irradiation up to a dose of 500 µC/cm2 does not accelerate quasi-breakdown of ultra-thin gate oxide.

X-ray irradiation effect on the reliability of ultra-thin gate oxides and oxynitrides

During X-ray irradiation of MOS devices, interface states as well as bulk electron and hole traps are generated at the Si SiO 2 interface and in the SiO 2 layer respectively. In this paper, we investigate the effect of X-ray irradiation on the electrical characteristics of 4.2 nm oxide and 4.4 nm oxynitride layers. It is shown that the bulk electron traps generated during irradiation lead to an increase of the gate current in the low gate voltage region, behaviour which can be attributed to trap assisted tunneling. From the analysis of time-dependent dielectric breakdown characteristics, it is demonstrated that the irradiation-induced bulk traps participate in the formation of the breakdown (percolation) path in the gate oxide layer.

Reliability of ultra-thin gate oxides grown in low-pressure N 2O ambient or on nitrogen-implanted silicon

The influence of nitrogen incorporated at the gate oxide interface on the reliability and electrical behavior of MOS capacitors was investigated. Incorporation of nitrogen was accomplished either by either rapid thermal oxidation (RTO) in N 2O or N 2O O 2 atmosphere at pressures between 75 to 500 mbar or by implantation of nitrogen at 20 keV and doses between 10 13 to 10 15 cm −2 into the substrate prior to RTO. Characterization of MOS capacitors with oxide thicknesses between 2.9 to 3.9 nm was achieved by reliability measurements at constant current or constant voltage stress, respectively. These measurements were correlated to the nitrogen dose at the gate interface which was determined by SIMS analysis. Stress reliability showed a sensitive dependence on the processing conditions. An accurate adjustment of the nitrogen dose at the gate interface is mandatory to attain improved reliability of nitrided oxides.

Dependence of Fermi level positions at gate and substrate on the reliability of ultrathin MOS gate oxides

In this work, we demonstrate that the reliability of ultrathin (<10 nm) gate oxide in MOS devices depends on the Fermi level position at the gate, and not on its position at the substrate for constant current gate injection (/spl upsi//sub g//sup -/). The oxide breakdown strength (Q/sub bd/) is less for p/sup +/ poly-Si gate than for n/sup +/ poly-Si gate, but, it is independent of the substrate doping type. The degradation of an oxide is closely related to the electric field across it, which is influenced by the cathode Fermi level for constant current injection. P/sup +/ poly-Si gate has higher barrier height for tunneled electrons, therefore, the cathode electric field is higher to give the same injection current density. A higher electric field gives more high-energy electrons at the anode, and therefore the damage is more at the substrate interface. We have also shown that oxide degradation is independent of the testing methodology, i.e., constant current or constant voltage stress. It depends mainly on the electric field in the oxide.