Reliability Of Integrated Circuits Research Articles

Trusted microelectronics: reverse engineering chip die using U-Net convolutional network

In the field of integrated circuits (IC) reverse engineering, accurate IC die image segmentation is critical for ensuring trust and detecting counterfeits. This study introduces a deep learning-based methodology utilizing a U-Net Convolutional Neural Network (CNN) tailored for IC image segmentation. Our model excels in processing complex IC images with noise, achieving superior segmentation accuracy. The model was evaluated on a dataset of 512 × 512 pixel IC die images, achieving a mean Intersection over Union (IoU) of 81.2%, which is a significant improvement over traditional image processing techniques that achieve an IoU around 65.3%. During training, the model’s Dice Loss showed a sharp decrease, as depicted in the provided graph, highlighting the model’s ability to effectively learn and refine segmentation boundaries. Simultaneously, the training accuracy, as illustrated in the accompanying accuracy graph, improved steadily, reaching approximately 60% but still rising. This convergence of Dice Loss and the upward trend in accuracy demonstrate the model’s robust performance across varying noise levels and its effectiveness in producing precise segmentation outputs. This work underscores the effectiveness of CNNs, particularly the U-Net architecture, in enhancing the accuracy and reliability of IC die image analysis, paving the way for improved IC manufacturing quality assurance.

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage.

The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition

In wafer map defect pattern recognition, deep learning methods are predominantly used. These models autonomously learn features without explicit human intervention due to their black-box type network architectures. While preceding feature extraction and modality representation may seem neglected in deep learning for wafer map defect pattern recognition, we addressed this question by proposing an innovative approach. Our proposed method employs an antecedent feature learning module to create a more compact and informative hash modality representation from input wafer maps. The method exceeds in achieving high recall, crucial for identifying actual defective wafers as much as possible in semiconductor manufacturing, where defects can impact integrated circuit functionality and reliability. Smaller-sized hash modalities against larger wafer maps allow the same model to speed up the process and require fewer computational resources.

Assembly of Large Flip Chip Die in Ceramic Packages

Hermetic packaging is required to ensure the reliability of processors and application specific integrated circuit (ASIC) chips that are used in strategic systems, whose operating lifetimes typically exceed thirty years. Performance requirements for emerging system applications are dictating the need for one thousand or more I/O, which precludes the use of wire bonded devices. These packaging requirements can be met by flip chip bonding die onto multilayer, high temperature cofired ceramic substrates. The hermetic environment is provided by a Kovar metal ring that is brazed onto the ceramic and sealed in the final assembly step, by welding on a metal cover. Several process and design requirements must be met to achieve high reliability flip chip assemblies. Reflowed devices must be free of flux residues because they are corrosive, provide a path for ion diffusion, are a source of moisture and degrade the adhesion of underfill to chip and substrate. Removal of flux residues by cleaning is problematic because the gap between chip and substrate is very small relative to chip area. A better approach is to bond chips without flux, as we do, by reflowing them in a formic acid environment. An important reliability requirement for strategic hardware is the ability to sustain many cycles over extended temperature ranges. Temperature cycles induce plastic deformation in the solder connections as a result of stresses generated by the mismatch in thermal expansion coefficients of the chip and package. These stresses can be reduced significantly by underfilling the bonded chip with a filled adhesive. Choice of material as well as process execution impact the effectiveness of underfill enhancement of reliability. Optimization of both the physical design and composition of the solder connections is essential to producing reliable flip chip assemblies. We make extensive use of finite element analyses (FEA) in which we track the accumulation of plastic strain energy in the solder connections as they are subjected to temperature cycle induced stresses. Good correlations between the energy accumulated per cycle and the number of cycles to failure can be achieved if accurate state models of the solder are used. We have a catalog of Anand models for the solder compositions that we use in our FEA simulations. One of the more challenging aspects of designing high performance flip chip packages is matching the size and pitch of the bond pads on the ceramic with those on the chip. Current devices use 90 micron diameter pads on 200 micron pitch, but newer designs are migrating towards 80 micron diameter pads on 180 micron pitch. It challenging to maintain tight tolerances on pad geometries in these higher density packages and to route all the additional signals. Thermal management is also an important component of the package design. Thermal vias and thermally conductive underfills are used to remove heat from the front side of the chip. On the backside of the chip, the gap between chip and cover is minimized and filled with a high thermal conductivity interface material. High fidelity FEA modeling is necessary to ensure that the chip can be adequately cooled in its hermetic environment. This paper discusses the impact of these design and assembly factors on the reliability of high performance, hermetically packaged flip chip assemblies.

Analysis Of the Development History, Key Technologies, And Future Development of Integrated Circuits

Integrated circuits (ICs) are pivotal in propelling the advancement of contemporary human technology. This article delves into the definition and evolution of integrated circuits, while also examining various collaborative technologies. Notable among these are EDR technology, VLSI testing technology, and High-Speed signal integrity testing assurance technology. The roots of integrated circuits can be traced back to their inception, with innovations occurring at a rapid pace over the years. EDR technology, for instance, has been instrumental in enhancing the efficiency of ICs by enabling data transmission at high speeds. Similarly, VLSI testing technology has played a crucial role in ensuring the reliability and quality of ICs. High-Speed signal integrity testing assurance technology has emerged as a fundamental aspect of IC development, ensuring that signals remain stable and accurate even at high speeds. These collaborative technologies have propelled ICs to new heights, paving the way for more powerful and efficient electronic devices. Furthermore, this article explores the challenges and prospects associated with integrated circuits on both a national and global scale.

Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA.

Most of the latest generation of integrated circuits use FinFET transistors for their performance, but what about their reliability? Does the architectural evolution from planar MOSFET to FinFET transistor have any effect on the integrated circuit reliability? In this article, we present a test bench we have developed to age and measure the degradation of 5103 ring oscillators (ROs) implemented in nine FPGAs with 16nm FinFET under different temperature and voltage conditions (Vnom≤Vstress≤1.3Vnom and 25°C≤Tstress≤115°C) close to operational conditions in order to predict reliability regarding degradation mechanisms at the transistor scale (BTI, HCI and TDDB) as realistically as possible. By comparing our initial RO measurements and the data extracted from Vivado, we will show that the performance of the nine FPGAs is between 50% and 70% of the best performance expected by Vivado. After 8000 h of ageing, we will see that the relative degradations of the RO are a maximum of 1%, which is a first indicator proving the FPGAs' good reliability. By comparing our results with similar studies on 28 nm MOSFET FPGAs, we will reveal that 16 nm FinFET FPGAs are more reliable. To be implemented in an FPGA, an RO uses logic resources (LUT) and routing resources. We will show that degradation in the two types of resources is different. For this reason, we will present a method for separating degradations in logical and routing resources based on RO degradation measures. Finally, we will model rising and falling edge propagation time degradations in an FPGA as a function of time, temperature, voltage, signal duty cycle and resources used in the FPGA.

Electromigration-Aware Memory Hierarchy Architecture

New mission-critical applications, such as autonomous vehicles and life-support systems, set a high bar for the reliability of modern microprocessors that operate in highly challenging conditions. However, while cutting-edge integrated circuit (IC) technologies have intensified microprocessors by providing remarkable reductions in the silicon area and power consumption, they also introduce new reliability challenges through the complex design rules they impose, creating a significant hurdle in the design process. In this paper, we focus on electromigration (EM), which is a crucial factor impacting IC reliability. EM refers to the degradation process of IC metal nets when used for both power supply and interconnecting signals. Typically, EM concerns have been addressed at the backend, circuit, and layout levels, where EM rules are enforced assuming extreme conditions to identify and resolve violations. This study presents new techniques that leverage architectural features to mitigate the effect of EM on the memory hierarchy of modern microprocessors. Architectural approaches can reduce the complexity of solving EM-related violations, and they can also complement and enhance common existing methods. In this study, we present a comprehensive simulation analysis that demonstrates how the proposed solution can significantly extend the lifetime of a microprocessor’s memory hierarchy with minimal overhead in terms of performance, power, and area while relaxing EM design efforts.

Thermal and mechanical reliability of thermal through-silicon vias in three-dimensional integrated circuits

This research aims to explore the influences of shapes, structures, and arrangements of thermal through-silicon vias (TTSVs) on the thermal and mechanical reliability of a three-dimensional integrated circuit (3D IC). For this purpose, a finite element model coupling the temperature and stress fields in a representative 3D IC with three layers of dies was established to allow numerical simulation of thermal and mechanical reliability caused by the above three factors. The research results show that firstly, rectangular TTSVs have better heat transfer performance than commonly used circular TTSVs of the same area. However, the former is more likely to cause problems pertaining to mechanical reliability in dies. Secondly, compared with the in-line mode of arrangement, the staggered arrangement mode can enable the more compact and uniform arrangement of TTSVs and improve the capacity for heat conduction between adjacent TTSVs, thus reducing the hotspot temperature: meanwhile, the thermal stress rises giving rise to a contradiction between the conventional means of enhancing the heat transfer performance of TTSVs and the resulting increase of thermal stress. Finally, by adding air gaps to TTSVs, the thermal stress around TTSVs can be reduced, while the heat transfer performance also decreases. If air gaps are replaced with carbon nanotubes (CNTs), such a problem can be alleviated. The analysis methods and research results can provide an important reference for the trade-off between thermal reliability and mechanical reliability in 3D ICs in engineering practice.

Development and Challenges of Reliability Modeling From Transistors to Circuits

The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.

ОБЗОР ЛАЗЕРНЫХ СКАНИРУЮЩИХ МЕТОДОВ ИССЛЕДОВАНИЙ МИКРОЭЛЕКТРОННЫХ ПОЛУПРОВОДНИКОВЫХ СТРУКТУР

The development and widespread of high-tech microelectronic products impose increased requirements on the quality and reliability of microcircuits. The most effective methods for reliability improvement of electronic systems include diagnostic non-destructive testing (NDT) methods and selective destructive testing in special cases. Studies using visual inspection and electrical testing, consisting of functional and parametric testing, do not provide enough information to detect latent defects (for example, macro-defects in SiO 2 layers in CMOS chips) and to detect fakes and counterfeits. A fake integrated circuit (IC) may contain an undeclared malicious modification of the circuit, called hardware bugs. The common ICs studying tools are systems based on microfocus X-ray sources, scanning acoustic microscopes, optical and scanning electron microscopes, and X-ray fluorescence spectroscopes. Products destruction avoidance is a fundamental point, for example, for the technological process control in crystal manufacturing. Investigation of ICs using a light microscope is one of the most accessible and widespread method of microchip NDT. Semiconductor ICs structure scanning from the side of the device layer is limited by the shielding effect of metallization, since the metal is opaque for light. This limitation can be overcome by an alternative approach to microchip scanning based on irradiating the IC from the side of the substrate with laser sources in the near-IR range. This paper provides a brief overview of the major methods used in laser scanning microscopy to analyze the structures, responses, and features of the operating modes of semiconductor circuits. The main advantages and limitations in the use of optical methods are described, as well as what information about the product can be obtained as a result of laser scanning.

A general approach for degradation modeling to enable a widespread use of aging simulations in IC design

The importance of integrated circuit (IC) reliability has been growing to benefit from the potentials of advanced semiconductor technologies in long-living applications, such as automotive electronics. Today, prototypes and products are tested for their reliability. The most important procedures are summarized in the industry standard AEC-Q100 for automotive ICs. There are indications that these tests will not be sufficient for future applications so that simulation-based reliability assessments are expected to complement them soon. Circuit-level aging simulations are one approach to virtually investigate the IC reliability before entering manufacturing. Although they have been available for years, they still appear rarely used. Despite significant progress in research and industry, degradation modeling and validation of aging simulations are still demanding and need improvements. This article focuses on degradation modeling and outlines challenges as well as a solution approach to establish aging simulations as a widespread verification step in future IC design projects.

Phase field simulation of healing and growth of voids in interconnects under electric field-induced interface migration

The micro-damage such as voids, inclusions, or cracks in interconnects of integrated circuits (IC) will evolve dramatically under different mass flow transport mechanisms driven by a variety of external physical fields, which will lead to the decrease of the reliability of the interconnects and the occurrence of failure in severe cases. Based on the microstructure evolution theory of solid materials, a phase field model under the mechanism of electric field-induced interface migration is constructed in this paper. The compatibility between the phase field model and the sharp interface model is proved by the asymptotic analysis. The modified theoretical solution of two-dimensional intragranular void in interconnects is derived, and the reliability of the finite element algorithm is verified by checking with the numerical results. Numerical simulation is carried out to discuss the effects of the electric field intensity χ, the initial morphological ratio β0, and the free energy density difference between the vapor-solid phase Δg˜ on the morphological evolution of the void. The results indicate that the external electric field drives the void to drift in the direction of the electric field, which is widely known as electromigration, and the morphology of the void becomes cylindrization gradually under the action of interface energy. With the increase of the external electric field, there are three morphological evolution trends of the void, including growth, equilibrium, and healing. The electric field critical value χcr, representing the equilibrium state of the void, is used to distinguish different evolution trends. The increase of β0 or the decrease of Δg˜ will lead to the acceleration of void drift velocity, the delay of cylindrization time, and the decrease of critical value, which aggravates the reliability problem of interconnects. Therefore, we should focus on the control of parameters such as χ, β0, and Δg˜, so that the current density of the interconnects is under the condition of χ<χcr. It can cause the intragranular void to shrink and even heal, effectively improving the reliability of IC and prolonging its service life.

Study on CDM ESD Robustness Among On-Chip Decoupling Capacitors in CMOS Integrated Circuits

The integrated circuit (IC) products fabricated in the scaled-down CMOS processes with higher clock rate and lower power supply voltage (VDD) are more sensitive to the transient/switching noises on the power lines with the parasitic inductance induced by the bonding wire. The typical method to suppress the power line noise is to add on-chip decoupling capacitors. Meanwhile, electrostatic discharge (ESD) is also a challenging issue on IC reliability in advanced CMOS technology. For the ICs fabricated in an advanced process, with the thinner gate oxide, the circuits are particularly vulnerable to the charged-device model (CDM) ESD events. However, there was very limited research to investigate the ESD robustness on the decoupling capacitors, especially during the CDM ESD events. In this work, the CDM ESD robustness among different types of decoupling capacitors in ICs was investigated in a 0.18- ${\mu }\text{m}$ CMOS technology.

Floorplanning for Area Optimization Using Parallel Particle Swarm Optimization and Sequence Pair

In the integrated circuit (IC) designing floorplanning is an important phase in the process of obtaining the layout of the circuit to be designed. The floorplanning determines the performance, size, yield, and reliability of VLSI ICs. The obtained results in this step are necessary for the other consecutive process of the chip designing. VLSI floorplanning from the computational point of view is a non-polynomial hard (NP-hard problem), and hence cannot be efficiently solved by the classical optimization techniques. In this paper, we have proposed a metaheuristic approach to address the problem by using the parallel particle swarm optimization (P-PSO) technique. The P-PSO uses a new greedy operation on the sequence pair (SP) to explore the search space to find an optimal solution. Experimental results on the Microelectronic Centre of North Carolina and Gigascale Systems Research Center benchmark shows that the applied parallel PSO (P-PSO) may be used to produce an optimal solution.

An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using α-Power MOSFET Model

Aggressive technological scaling continues to drive ultra-large-scale-integrated chips to higher clock speed. This causes large power consumption leading to considerable thermal generation and on-chip temperature gradient. Though much of the research has been focused on low power design, thermal issues still persist and need attention for enhanced integrated circuit reliability. The present paper outlines a methodology for a first hand estimating effect of temperature on basic CMOS building blocks at ultra deep submicron technology nodes utilizing modified α-power law based MOSFET model. The generalized α-power model is further applied for calculating Zero Temperature Coefficient (ZTC) point that provides temperature-independent operation of high performance and low power digital circuits without the use of conditioning circuits. The performance of basic digital circuits such as Inverter, NAND, NOR and XOR gate has been analyzed and results are compared with BSIM4 with respect to temperature up to 32nm technology node. The error lies within an acceptable range of 5-10%.

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

The history of integrated circuit (IC) development is another record of human challenges involving space. Efforts have been made to protect ICs from sudden malfunctions due to single-event effects (SEEs). These effects are triggered by only a single strike of particle radiation, such as an $\alpha $ -ray or cosmic ray, originating from our solar activity and galactic events including supernovas. This article explores how SEEs have evolved along with the progress in complementary metal-oxide-semiconductor (CMOS) digital IC technology, or device scaling, from the early micrometer-scale generations to the current nanometer-scale generations. For this purpose, focusing on basic digital elements, that is, inverters and static random access memories (SRAMs), this study collected more than 100 sets of data on four characteristic parameters of single-event upsets (SEUs) and single-event transients (SETs), both of which are undesired flips in digital logic states. The results show that all the examined parameters, such as the SEU critical charge, decrease with the device feature size. Analysis involving structure classification, such as bulk versus silicon-on-insulator (SOI) substrates and planar versus fin channels, reveals relationships between the examined SEE parameters and other device features such as the power supply voltage. All the data collected in this survey are explicitly given in tables for future exploration of IC reliability.

Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing

Studies on further IC development mutually predict that the reliability of future integrated circuits (ICs) will be severely endangered by the occurrence of electromigration (EM). The reason for the increasing number of EM damages are the ongoing structural reductions in the IC. Digital circuits are particularly at risk because they have been neglected in the consideration of EM, resulting in a lack of suitable EM measures. For this reason, a paradigm shift in physical design must be accomplished, complementing the traditional EM verification step after layout creation with a proactive EM-robust physical synthesis. This work presents the necessary adaptations and new approaches by modifying the routing step of digital circuits, resulting in an EM-robust routing result. Our contribution includes the development of EM models, the derivation of EM-suppressing measures, and finally the consideration of these countermeasures in an EM-robust routing process. In summary, our work is an important contribution to increase the EM robustness in digital layouts, thereby ensuring the reliability of future ICs.

Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit.

A flexible Si complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) with multi-level interconnects is realized by thinning down and transferring the CMOS IC onto a polymer substrate. A detailed mechanical and electrical reliability analysis of the flexible Si CMOS IC is carried out in relation to the neutral mechanical plane (NMP) that is extracted from both analytical and numerical modeling. To enhance the reliability by optimizing the NMP position, the thicknesses of all the layers in the CMOS IC on the polymer substrate are carefully adjusted. The NMP-optimized flexible Si CMOS IC maintains its mechanical and electrical stability even at a 5-mm radius bending condition. In addition, to explore the degradation mechanism of the flexible Si CMOS IC, the change of the interface state density of the flexible Si CMOS at different bending conditions is investigated using the charge pumping method. Finally, the long-term electrical reliability of this flexible Si CMOS IC is also investigated.

Combined ionizing radiation & electromagnetic interference test procedure to achieve reliable integrated circuits

International standards have been proposed and used to test Integrated Circuits (ICs) for Total-Ionizing Dose (TID) and Single-Event Upset (SEU) as well as for Electromagnetic Interference (EMI). Nevertheless, these standards are separately applied to the IC or electronic system, one after the other, and do not take into account the combined effects of these types of radiation may take over the ICs. In more detail, there is no standard that rules combined tests for TID, SEU and EMI. This paper aims to fulfill this lack of product quality information and proposes a new methodology to improve the reliability of ICs by performing combined tests for TID, SEU and EMI. We also present recent experimental results from combined measurements that we performed on a commercial FPGA IC widely used in critical embedded applications such as aerospace and automotive. Such results strongly suggest that the effects of radiation are not negligible and should be taken into account if one intends to design reliable embedded systems.