Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing

Abstract

Studies on further IC development mutually predict that the reliability of future integrated circuits (ICs) will be severely endangered by the occurrence of electromigration (EM). The reason for the increasing number of EM damages are the ongoing structural reductions in the IC. Digital circuits are particularly at risk because they have been neglected in the consideration of EM, resulting in a lack of suitable EM measures. For this reason, a paradigm shift in physical design must be accomplished, complementing the traditional EM verification step after layout creation with a proactive EM-robust physical synthesis. This work presents the necessary adaptations and new approaches by modifying the routing step of digital circuits, resulting in an EM-robust routing result. Our contribution includes the development of EM models, the derivation of EM-suppressing measures, and finally the consideration of these countermeasures in an EM-robust routing process. In summary, our work is an important contribution to increase the EM robustness in digital layouts, thereby ensuring the reliability of future ICs.