Reference Clock Frequency Research Articles

Design and Simulation of Clock Divider using VHDL

This paper presents the diesign and simulation of clock divider circuit using VHDL(VHSIC Hardware Description Language) on an FPGA(Field Programmable Gate Array). The clock divider circuit is a fundamental component in digital system for generating lower frequency clocks from a higher frequency reference clock. The paper starts up with simple divider where the clock is divided by even numbers, odd numbers and then later expands it into non- integer dividers. Keywords:- clock divider, D flipflop, FPGA

Current status and applications of time-to-digital converters

Time-to-Digital Converter (TDC) is widely used to realize time interval measurement. The high-precision time measurement technique has important applications in the fields of laser ranging, particle identification, and radioactive nuclear medicine engineering. Based on the existing literature research and data, this paper studies the application areas of TDC in the present development and analyzes the future prospects of TDC applications. The research results showed that: TDC, based on signal screening, realizes time interval measurement as the ultimate purpose of building the system and, at the same time, completes the function of multi-pulse time interval measurement, which can meet the needs of more diversified measurements in the experiments. In the circuit structure, it can identify the feedback output in the all-digital phase-locked loop (ADPLL) and the reference clock phase and frequency information between the feedback output and the reference clock in an ADPLL. It is also promising for use in other areas of high-precision time measurement and processing of circuit signals.

A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.

New Clock Distribution System Based on Clock-Duty-Cycle-Modulation for Distributed Data-Aquisition System

This paper presents a clock distribution system based on a clock-centric modulation technique called clock-duty-cycle-modulation (CDCM) using the IOSERDESE2 primitives of Xilinx field programmable gate array (FPGA). The implemented CDCM techniques, CDCM-10-1.5 and CDCM-10-2.5, transfer 1-bit and 2-bit data per clock cycle by changing the trailing edge positions, respectively. This is the first work to succeed transmitting multi-bits per clock cycle by the CDCM. The developed system consists of the CDCM-based transceiver and the link layer protocol. All the components are implemented using the regular bunk functions in FPGA. The system is independent from a FPGA high-speed serial transceiver and does not require a clock data recovery circuit. In this work, two clock generators were utilized for clock recovery; one is a jitter cleaner IC, CDCE62002 from Texas Instruments, and the other is mixed-mode clock manager (MMCM) in FPGA. The 8-bit incremental data was transmitted by the CDCM modulated clock signal through an optical fiber. The jitters of the clock signals recovered by CDCE62002 were 5.8 and 6.8 ps in standard deviation for CDCM-10-1.5 and CDCM-10-2.5, respectively, when the reference clock frequency was 125 MHz. The averaged phase change of the recovered clock signal during the data transmission was smaller than 10 ps with respect to the clock phase recovered from the signal with the duty cycle of 50%. The obtained bit-error-rate (BER) was smaller than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

A low jitter fractional PLL with offset current charge pump

A low jitter fractional phase-locked loop (PLL) with high quality local oscillator signal for RF transceiver is presented in this paper. Compared with the traditional structure, not only the gated-offset linearization technique is adopted to improve the linearity of the charge pump (CP), but also the sampling filter is used to further reduce the output ripple of the charge pump. The voltage-controlled oscillator (VCO) adopts the tail resistor and second harmonic filter structure to reduce its noise level. The circuit is implemented in a standard 28 nm CMOS process, and the reference clock frequency is 95.76 MHz, which is provided by an integrated crystal oscillator. The chip test results show that the locking frequency range of the PLL is located between 2.42GHz and 3.27 GHz. The phase noise measured at the center frequency of 3.27 GHz at 1 MHz frequency offset is −122 dBc/Hz, RMS jitter is 286 fs, the chip area is 0.78 mm2, and the core current consumption of the PLL is 67.2 mA.

A Wide-Dynamic Range (-40 °C to 180 °C) Active Wireless MEMS Temperature Sensor With 7m °C Sensitivity

We demonstrate a highly-accurate active wireless microelectromechanical (MEMS) temperature sensor with the largest reported dynamic range (-40°C to 180°C) among active MEMS temperature sensors. The sensor uses a 27.2 MHz high quality factor (Q > 3,200) AlN-on-Si thin-film piezoelectric-on-silicon (TPoS) MEMS resonator to enable highly accurate temperature sensing, with minimum sensitivity (S), better than 0.011 °C across this wide temperature range. The wireless sensor uses an innovative frequency shift keying (FSK) 900 MHz direct up-conversion transmitter. The transmitter uses frequency multipliers for up-conversion, obviating the need for a temperature-stable frequency reference clock, thereby preserving the temperature coefficient of frequency (TCF) of the resonator, and consequently the sensitivity of the sensor. The experimental results show a very high correlation (<0.03% error) between the TCF of the MEMS oscillator and that of the transmitter output signal, demonstrating the viability of the proposed direct up-conversion technique. A detailed analysis of the Allan variance for MEMS temperature sensors which can be used to design for a given minimum sensitivity, is also presented in the paper.

A 2.5–5.0-GHz Clock Multiplier With 3.2–4.5-mUIrms Jitter and 0.98–1.06 mW/GHz in 65-nm CMOS

We present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.0625MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0 GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 156.25-312.5MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 2.5-5.0 GHz output frequency with 0.98-1.06mW/GHz power dissipation.

Time-Expanded Φ-OTDR Based on Binary Sequences

In this letter, the capabilities of time-expanded phase-sensitive optical time-domain reflectometry (TE <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Phi $ </tex-math></inline-formula> -OTDR) using binary sequences are demonstrated. We present a highly flexible and integrable TE <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Phi $ </tex-math></inline-formula> -OTDR approach that allows a customized distributed optical fiber sensor (range, spatial resolution, and acoustic sampling) by simply changing the length of the binary sequence and the reference clock frequencies of the binary sequence generators. The here presented architecture eliminates the need for the cumbersome arbitrary signal generators used to date to create the dual-comb spectra for interrogating the fiber. In this approach, the use of large binary sequences allows us to obtain dual combs in a simple and cost-effective way. Spatial resolution of ~1 cm is achieved, attaining ~15,000 independent measurements points along the interrogated fiber, with a capability of sensing ~30,000 measurements points.

A low power clock generator 400–1800 MHz for ADPLL

This paper describes a low-power all-digital clock generator (ADCG) designed for reading and processing signals from detectors of large physical experiments. The clock generator operates with a reference clock frequency of 10 to 50 MHz and generates an output signal ranging from 400 to 1800 MHz in 10 MHz steps. The clock generator has been approved in 28 nm CMOS technology of TSMC. The power consumption and chip area of the block are 1.5 mW and 80 × 80 μm2 correspondingly. A wide range of reference and output frequencies makes this block versatile in application.

A high frequency builder software for arbitrary radio frequency signals.

While the frequencies accessible by signal generators steadily rise, the synthesization of complex and arbitrary waveforms with high frequency components remains challenging, especially when restricted by an external reference clock. In this article, we present a comprehensive software package combined with state-of-the-art hardware as a solution for the generation of highly sampled, arbitrary radio frequency waveforms. The software can be used to conduct both synchronous and heterodyne pump-probe experiments due to a variety of different synchronization modules. While both kinds of modules allow for standard waveforms, such as sines, pulses, and bursts, as well as any arbitrary signal, the heterodyne modules additionally are not restricted by the reference clock frequency. Both the output and the synchronization module can be adapted to support additional measurement devices. Due to the modular software structure, individual classes can be exchanged while maintaining all functionalities. The software provides a user friendly graphical interface that allows us to compose, save, and load complex arbitrary waveforms within only a few steps. The frequency selectivity provided by the software-hardware combination allows us to directly target specific excitation states of physical systems. Conducting a heterodyne scanning transmission x-ray microscopy experiment, we are able to demonstrate the capabilities of the software when paired with a high sample rate arbitrary waveform generator. The heterodyne synchronization modules allow for unlimited flexibility leveraging arbitrary waveform generation to their full power. By solving the challenges of synthesizing highly complex electromagnetic waves, the software enables a large variety of experiments to be performed more conveniently.

A 3.2-GHz 405 fsrms Jitter –237.2 dB FoMJIT Ring-Based Fractional-N Synthesizer

A ring-oscillator (RO)-based low-jitter digital fractional-N frequency synthesizer is presented. It employs a frequency doubler (FD) that doubles the reference clock frequency, a 2-bit time-to-digital converter (TDC) with optimized thresholds to minimize the quantization error, and a high-resolution digital-to-time converter (DTC) to cancel the quantization error of the delta-sigma fractional divider (FDIV). DTC’s linearity is improved using a piecewise linear (PWL) function-based correction scheme. On-chip digital calibration is extensively used to correct imperfections of the FD, TDC, and DTC. A prototype synthesizer incorporating the proposed techniques and implemented in a 65-nm CMOS produces a 3.2-GHz output clock from a 96-MHz input clock. The worst-case integrated jitter is 306 and 405 fs in integer and fractional-N modes, respectively. The synthesizer consumes 11.7 mW from a 1-V supply of which 7.84 mW is consumed by the oscillator. The jitter figure-of-merit of the synthesizer is −237.2 dB.

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop

An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear approximation and z-domain PN model are utilized to simplify the analysis with excellent agreement between the time-domain simulation and z-domain approximation. The influences of the asymmetric waveform, flicker noise corner, frequency error and reference noise are also discussed and then ignored based on the reasonable approximation. Under a given process, reference clock frequency and supply voltage, the ideal FOM can be derived theoretically. Based on these insights, the predicted FOM can be the benchmark metric in the design of MDLL for the possible best jitter-power performance.

Improved Complex Receiver System Design Strategies to Overcome EMI/EMC Challenges

This article analyzes various strategies and implementation techniques in detail for complex receiver system design to qualify Environmental Stress Screening (ESS) especially EMI/EMC tests for airborne system applications. Isolation of leakage energy between various RF/DC-DC converters/regulators/pulsing blocks are the key target of this design to keep conductive and radiative emission to a minimum. Hence, complex receiver design has been segregated into various modules. Then they are stacked together very tactfully within the specified area without compromising inter-channel/module interference between them and the form factor, respectively. The super compact stacks are further channelized for RF, DC supply, controls etc. and protected from any kind of interference. Low cost flexi interconnects are made to interface various stacks to arrest unwanted high/low frequency leakages. Proper layout, component placement, layer specific signal routing, and wire shielding have been used to protect low/high frequency reference clock, control signals, switching pulses, etc. from mixing. Processor boards with a DC supply unit are also integrated into the receiver as another stack and have been isolated from each other to qualify emission tests. Finally, four modules are developed and tested over temperatures of -40°C to +71°C (ESS) and EMI/EMC successfully to establish the methodology for mass production.

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

FM-CW compact reflectometer using DDS signal generation

A prototype of a compact coherent fast frequency sweeping RF back-end is being developed at IPFN-IST using commercial Monolithic Microwave Integrated Circuits (MMIC). On this work we present the usability of this concept of compact reflectometry associated with a Direct Digital Synthesis (DDS) source. Flexibility is one of the design goals for the back-end prototype, so that it can easily match the required frequency range. The backend alone covers the NATO J-band (10 GHz to 20 GHz) and is designed to drive external full band frequency multipliers, resulting in an ultra-wideband coverage of up to 140 GHz. FM-CW radar precision is strongly dependent on the probing source linearity. DDS nowadays plays an important role in signal generation in many fields of applications for communication systems as well as in radar technology. Modern DDSs are fully integrated, low-cost, single chip solutions that only need an external clock source for generating sinusoidal output signals up to several gigahertz. The DDS benefits from the totally digital generation of the output signal, which allows full control of the signal’s frequency and phase, both with very high precision and resolution. Recent implementations feature automatic sweeping capability, thus allowing the DDS to generate very linear and agile frequency chirps, assuming a high quality and constant frequency reference clock source. We propose to implement a DDS signal generation solution with the capability of a full band sweep in 1 μs. On the receiver side the IF and reference signals will be digitised allowing the use of high flexible data processing techniques. Input/output signals will allow the synchronisation of several systems.

Phase-locked Loop with True Random Number Generator for Reference Spur Reduction

This paper presents a phase-locked loop (PLL) that reduces reference spurs by using a true random number generator (TRNG). In conventional PLLs, a frequency component of the reference clock appears spurious tones in the voltage-controlled oscillator (VCO) output. In the proposed PLL, the TRNG randomly delays UP/DOWN signals which result in inconsistent timing of charging/discharging at the output of the charge pump (CP). As a result, the CP output disperses the reference spur of the VCO output by making the reference clock frequency component uneven. The proposed PLL was fabricated in a 180-nm CMOS technology. It dissipates 23 mW at 2-GHz with 1.8-V supply and achieves more than 23 dB of additional spur suppression.

Dynamic Clock Skew Estimation and Fusion Acquainted with Environmental Factors

Clock skew reflects the drift rate of a clock w.r.t. the nominal or reference clock frequency, which is the root cause of clock drifting. However, as the output of clock is largely affected by some environmental factors. Therefore, clock skew estimation is particularly difficult in wireless sensor networks (WSNs), as the working environments of WSN are usually dynamic, unpredictable or even hazard. Besides, sensors are usually powered by batteries with limited communication and computation capacity. The clock skew is found to be non-stationary containing severe measurement and process noises. Thus, we attempt to jointly consider the environmental factors into the clock skew estimation using Kalman filter. We propose to use the change of temperature and/or voltage to enhance the clock skew estimation performance. Besides, in multi-hop wireless networks, where the synchronization is done in a hierarchical procedure, one node may have the chance to receive more than one timestamps. Therefore, we propose to use the information fusion technique to dynamically combine the information contained in different timestamps to promote the clock skew estimation accuracy. Besides, we further derive the statistic lower bound of estimation errors, which can serve as a benchmark. The performance of the proposed schemes have been verified by extensive simulation results, where the root mean square error (RMSE) can be reduced by around 60% when compared with the previous solutions.

A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%.

Design of a spurious-free RF frequency synthesizer for fast-settling receivers

A tunable reference clock frequency topology is presented as a spur reduction application for frequency synthesizers of fast frequency hopping spread spectrum systems. The method was verified by measurements on a designed hardware operating at L-band frequencies. This spur reduction method is based on optimizing the reference clock frequency of synthesizers to mitigate spurs. By using the spur reduction method, the power of spurious signals was reduced up to 57 dB. The performance of the spur reduction method was also analyzed at different loop-filter configurations. Smaller lock time was obtained by enlarging the bandwidth of the loop filter up to 150 kHz. The required power response of the spurious signals specified in telecommunication standards was achieved even though the loop filter bandwidth was enlarged.

A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC -based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of −104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times $ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm2 and consumes 40 mW.