A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance

Abstract

Ring oscillator (RO)-based frequency synthesizers have been widely used in Systems on Chip (SoCs) due to their tiny active area and broad tuning range. However, they also experience significant spur and jitter. Based on an extensive evaluation of the factors of space, power usage, reference clock frequency, jitter, and reference spur. In order to achieve low jitter and low spurious, we present a time-to-voltage conversion phase-locked loop (TVC-PLL) based on a RO in this study. To achieve a wide range of adjustable phase-detection gain, we introduce a time-to-voltage converter (TVC-PD) as a phase detector. We suggest a pre-phase locked module based on orthogonal output clocks help with locking in order to address the problem of the limited phase detection range of conventional TVCs, which can only be used for frequency-locked loops (FLLs). According to simulation results, our suggested TVC-PLL is built using TSMC 65-nm CMOS, uses 4.053 mW of power, and occupies an active area of 0.024 mm2 at a working frequency of 2.4 GHz. It achieves an RMS jitter of 625.4 fs in the 10k to 100MHz frequency range, a reference spur of −77.7 dBc, and a figure-of-merit (FoMJ) of −238.0 dB.