Spur Minimization Techniques for Ultra-Low-Power Injection-Locked Transmitters

Abstract

Frequency multiplying wireless transmitters (TX) employing harmonic injection-locked technique benefit from high energy efficiency and less hardware complexity but largely suffer from reference spurs that violate the TX spectral specifications. This work proposes a self-aligned phase-locked loop (PLL) in conjunction with harmonic injection locking technique to achieve significantly improved spur performance under ultra-low-power (ULP) operations for sub-GHz IoT TXs. The on-chip type-I PLL calibrates the phase error in the ring oscillator (RO) in real-time and avoids large spurs induced from the frequency deviation in the harmonic injection locking. A compact zero power consumption twin-T notch filter for spur suppression is implemented within the PLL loop to tackle the rail-to-rail voltage jump that comes from the output of the phase detector (PD). Designed and fabricated in the TSMC 180 nm CMOS process, the proposed frequency multiplying TX occupies an active area of only 0.0413 mm2. The lowest power consumption with >3X improved energy-efficiency is observed while consistently achieving >62 dB spur suppression with −14 dBm output at 915 MHz. The TX supports OOK modulation with an average power consumption of $200.9~\mu \text{W}$ only at 3 Mb/s data rate achieving a normalized 66.97 pJ/bit energy efficiency.