Reference Clock Frequency Research Articles

Phase Noise in Modular Millimeter Wave Massive MIMO

This paper investigates the effect of oscillator phase noise on a multiuser millimeter wave (mmWave) massive MIMO uplink as we scale up the number of base station antennas, fixing the load factor, defined as the ratio of the number of simultaneous users to the number of base station antennas. We consider a modular approach in which the base station employs an array of subarrays, or “tiles.” Each tile supports a fixed number of antennas, and can therefore be implemented using a separate radio frequency integrated circuit (RFIC), with synchronization across tiles accomplished by employing a phased locked loop in each tile to synthesize an on-chip oscillator at the carrier frequency by locking on to a common lower frequency reference clock. Assuming linear minimum mean squared error (LMMSE) multiuser detection, we provide an analytical framework that can be used to specify the required power spectral density (PSD) mask for phase noise for a target system performance. Our analysis for the phase noise at the output of the LMMSE receiver indicates two distinct effects: self-noise for each user which is inversely proportional to the number of tiles, and cross-talk between users which is insensitive to the number of tiles, and is proportional to the load factor. These analytical predictions, verified by simulations for a 140 GHz system targeting a per-user data rate of 10 Gbps, show that tiling is a robust approach for scaling. Numerical results for our proposed design approach yield relatively relaxed specifications for phase noise PSD masks.

A Novel Low Power, Minimal Dead Zone Digital PFD for Biomedical Applications

Chronic diseases and rising aging populations are the major reasons towards the usage of low power, low noise, life time performance Biomedical Implantable Devices. Efficient architectural designs will be responsible for the requirements set out above. This paper focuses on the ADPLL DPFD architecture for implantable biomedical devices. For high performance DPFD, the dead zone, lock in time is a seldom limitation to ADPLLs. In the present paper, a new approach to design a dead zone free with fast and high locking time and low phase noise DPFD is considered to be a challenge. This can be accomplished by carefully controlling the reference and feedback clock frequencies of the phase detector with the proposed NIKSTRO/SURAV latch based sense amplifier. The proposed architecture was developed and simulated using 45nm technology and it is observed that it provides a 20ns dead zone with 4.8mW of power consumption at the rate of 1.8GHz, while the lock in time for the proposed method is 340ns with moderate phase noise. It is also noted that the designed one showed better results when compared to the existing ones.

A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching

The enhancement in the settling response of frequency synthesizers would open up prospects for new applications such as spread spectra and frequency hopping systems. Toward deriving a methodology for a fast settling response, we present a switched-loop digital phase locked loop (DPLL) incorporating an integral-derivative controller-based subsystem. The dominant features accelerating the settling response with low jitters in this DPLL are: 1) hybrid phase detection with a state machine using differential and double integration filtering effect and 2) a time-interleaved direct digital synthesizer (DDS)-based digital-to-time converter (DTC) with stable-edge sampling. A 5-GHz fractional- $N$ DPLL (FNDPLL) has been implemented in CMOS 65-nm-LL technology with the proposed technique of loop-order switching. The measured results of the implemented FNDPLL highlight that the system is capable of fastest reported frequency settling to ±25-ppm error within 1.5 ${\mu }\text{s}$ , using a reference clock frequency of 100 MHz. With one-time calibration, the downsampled output of DDS array-based phase interpolator achieves an integral nonlinearity (INL) of 0.25 ps, as a fractional divider in the loop.

Charge controlled delay element enabled widely linear power efficient MPCG‐MDLL in 1.2V, 65nm CMOS

SummaryIn this work, a robust, low‐power, widely linear multiphase clock generation and multiplying delay‐locked loop (MPCG‐MDLL) architecture is realized, using a new differential charge‐mode delay element circuit topology. The heart of any MPCG‐MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG‐MDLL, in terms of its specifications such as peak‐to‐peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight‐phase MPCG‐MDLL along with the charge‐mode delay element outperforms the conventional MPCG‐MDLLs that deploy delay elements such as a current‐starved inverter (CSI), wide‐range CSI, triply controlled delay cell, digital‐controlled delay element, and the like. The eight‐phase MPCG‐MDLL along with the new charge‐mode delay element circuit topology is implemented in 1.2‐V, 65‐nm CMOS technology. The performance results show that the eight‐stage delay line has a delay range from 640 to 960 ps over the rail‐to‐rail control voltage range. The implemented MPCG‐DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak‐to‐peak jitter of less than 60 fs for all the DLL output phases and peak‐to‐peak jitter of 0.54 and 1.24 ps for the synthesized 5‐GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG‐MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm2.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Fixed‐frequency hysteretic buck converter with novel adaptive window control and transient response improvement

This study presents a fixed-frequency hysteretic buck converter designed and fabricated using 0.18-µm complementary metal–oxide–semiconductor process. With a phase-locked loop (PLL)-based adaptive window control, the proposed buck converter can achieve a fixed switching frequency, and this frequency can be tuned within a certain range through a reference clock frequency. Concurrently, a novel auxiliary circuit is proposed to monitor the converter's output loading dynamics to reduce the converter's transient recovery time. It will also help to regulate the output voltage at the steady-state operation as well. With the supply voltage ranging from 3 to 4.2 V and an output voltage of 1.8 V, the simulated switching frequency is maintained at 10 MHz because of the PLL control. The transient response time is only 0.3 and 0.4 µs for a 400 mA step-up load and step-down load, respectively.

VCSEL-based Raman technology for extended reach time and reference frequency transfer systems

This paper experimentally demonstrates a low-cost energy efficient alternative technique for long reach transfer of accurate reference frequency (RF) clock signals for extended reach RF distribution systems. This is achieved by adopting distributed forward Raman amplification and vertical cavity surface emitting laser (VCSEL) technology. A class 10G VCSEL is directly modulated with a 2 GHz RF clock signal. By exploiting a forward Raman pump with the flat gain of 8.6 dB, a 100.8-km-long standard single mode fiber (SMF) RF clock distribution is experimentally achieved. A maximum phase noise of −117.66 dBc/Hz at offset frequency of 100 kHz and an RF clock jitter (RMS) of 5.36 ps is experimentally measured for 100.8-km-long fiber transmission without forward Raman amplification. However, with the adoption of forward Raman amplification, the measured phase noise and RMS improves to −86.59 dBc/Hz and 1.7 ps, respectively. Forward Raman pumping offers distributed high flat gain over a wide spectra range (over 35.5 nm), while VCSELs offer cost effective broadband signal distribution, therefore keeping the network optics investment low.

Simultaneous 45.2 Gbit/s 4-PAM data and 8 GHz reference frequency clock signal transmission over DWDM VCSEL channels for optical interconnects

In this paper, we propose and experimentally demonstrate a vertical cavity surface emitting laser (VCSEL)-based simultaneous 45.2 Gbit/s (2×22.6 Gbit/s) 4-PAM data and 8 GHz (2×4 GHz) phase modulated reference frequency (RF) clock signal transmission dense wavelength division multiplexing (DWDM) system for optical interconnects. Two low-cost power-efficient 10 G VCSEL channels with central wavelengths at 1 550.71 nm and 1 551.11 nm are separately modulated with 22.6 Gbit/s 4-PAM data, therefore doubling the channel bit rate. Carrier spectral efficiency per channel is further maximized by exploiting the phase attribute in transmission of a 4 Hz RF clock signal. To further maximize the network capacity, the two VCSEL channels are densely multiplexed at 0.4 nm spacing. We therefore experimentally achieve the network data rate of 45.2 Gbit/s with 8 GHz phase modulated RF clock signal. The results show that receiver sensitivities of −11.02 dBm and −9.98 dBm are experimentally achieved for VCSEL channels of 1 550.71 nm and 1 551.11 nm respectively without the phase modulated RF clock signal. However, the introduction of a phase modulated clock signal contributes to a maximum interference penalty of 0.57 dBm and 0.41 dBm for the considered channels respectively. Simultaneous distribution of transmission data and reference clock signal over shared network structure maximizes the carrier spectral efficiency and network capacity with low cost.

Multicast-enabled high-speed VCSEL technology for flexible data center networks

We experimentally demonstrate the multiple signal modulation on a single class 10 G vertical cavity surface emitting laser (VCSEL) carrier at 1 310 nm for next generation multicast-enabled data center networks. A 10 Gbit/s data signal is directly modulated onto a single mode VCSEL carrier. To maximize carrier spectral efficiency, a 2 GHz reference frequency (RF) clock tone is simultaneously modulated on the VCSEL phase attribute. The inherent VCSEL orthogonal polarization bistability with changing bias current is further exploited in transmission of a polarization based pulse per second (PPS) timing clock signal. Therefore, we simultaneously transmit a 10 Gbit/s directly modulated data, 2 GHz phase modulated RF and a polarization- based PPS clock signals using a single mode 10 GHz bandwidth VCSEL carrier. It is the first time that a single class 10 G VCSEL carrier is reported to transmit a directly modulated data, phase modulated RF clock and polarization based PPS timing signal simultaneously in a single wavelength. A of G.652 single mode fibre (SMF) transmission over 3.21 km is experimentally attained. A receiver sensitivity of −15.60 dBm is experimentally obtained for the directly modulated 10 Gbit/s data signal. A 3.21-km-long SMF transmission introduces a penalty of 0.23 dB to the data signal. The contribution of a 2 GHz phase modulated RF and a polarization-based PPS clock signal to this penalty is found to be 0.03 dB. An RF single- side band (SSB) phase noise values of −82.36 dBc/Hz and −77.97 dBc/Hz are attained without and with simultaneous directly modulated data and polarization-based PPS clock signals respectively for a 3.21-km-long SMF transmission. This work provides an alternative efficient and cost effective technique for simultaneous high-speed multiple information transmission to different network nodes within a data center network through shared network infrastructure.

DDFS and ΣΔ Approaches for Fractional Frequency Synthesis in Terahertz Instruments

This paper compares direct digital frequency synthesis (DDFS) and ΣΔ CMOS-based frequency synthesizers for terahertz instrument systems. This paper first discusses the need for fractional synthesis in terahertz systems, and provides a brief overview of reference clock frequency selection, and design choices related to implementation of fractional functionality. ΣΔ-multistage-noise-shape-based and DDFS-based fractional synthesis approaches and architectures are discussed and CMOS synthesizer modules based on both of these approaches are presented. Finally, the paper compares two different 100-GHz CMOS fractional frequency synthesizer chips, which employ the same millimeter-wave circuits but different fractional generators (third- and sixth-order ΣΔ, and DDFS-based). Performance in terms of phase-noise, spurious components, and power consumption are directly compared. Measurements suggest ΣΔ synthesis is more suitable than DDFS for THz fractional synthesizers due to the high-phase multiplication of spurs.

A low temperature drift coefficient crystal-less frequency reference clock compensated by temperature sensor for microsystem

Quartz oscillator has been widely used as reference clock source in the microsystems due to its good performance. But a good crystal oscillator costs too much and its bulky size is not desired. This paper aims at designing an alternative integrated oscillator to replace the external quartz oscillator. The proposed circuit used maneatis delay cell to construct a ring oscillator for its superior linear I–V characteristic. As for a frequency reference clock, its frequency stability over temperature is required at first. After detailed mathematical deducing and careful analysis, a formula is proposed to describe the relationship between desired control voltage and temperature by assuming the frequency as constant. This paper utilized bipolar transistor as the temperature sensor, combining it with CTAT current source and resistor to create a first-order temperature compensation control voltage. The chip with typical frequency of 10 MHz was fabricated in a 0.35 [Formula: see text]m CMOS technology and occupied 0.45 mm2. The measured results show that the frequency variation is ±0.2% for supply changes from 4.8 V to 5 V, and frequency variation is 48 ppm when the temperature change is from −40[Formula: see text]C to 85[Formula: see text]C, while the average current of the tested chip consumes 50 [Formula: see text]A from 5 V.

Study on Integrated Technique of Laser Ranging and Communication and Its Applications in Deep Space

The current development of integrated technique of laser ranging and communication is introduced. A new integrated technique of high precision laser ranging and high speed communication is presented based on dual one-way ranging(DOWR)and BPSK modulation heterodyne coherent detection. A symbol phase ranging method is applied to achieve the integrated system design,and the ground experiments are developed. The results show that the data rate of laser link reaches 1 Gbit/s and the ranging precision is better than 0.9 mm. The influence of reference clock frequency difference on ranging precision is analyzed. Finally,future applications of the integrated laser ranging and communication system in deep space exploration are expected.

A high capacity data centre network: simultaneous 4-PAM data at 20 Gbps and 2 GHz phase modulated RF clock signal over a single VCSEL carrier

Optical fibre communication technologies are playing important roles in data centre networks (DCNs). Techniques for increasing capacity and flexibility for the inter-rack/pod communications in data centres have drawn remarkable attention in recent years. In this work, we propose a low complexity, reliable, alternative technique for increasing DCN capacity and flexibility through multi-signal modulation onto a single mode VCSEL carrier. A 20 Gbps 4-PAM data signal is directly modulated on a single mode 10 GHz bandwidth VCSEL carrier at 1310 nm, therefore, doubling the network bit rate. Carrier spectral efficiency is further maximized by modulating its phase attribute with a 2 GHz reference frequency (RF) clock signal. We, therefore, simultaneously transmit a 20 Gbps 4-PAM data signal and a phase modulated 2 GHz RF signal using a single mode 10 GHz bandwidth VCSEL carrier. It is the first time a single mode 10 GHz bandwidth VCSEL carrier is reported to simultaneously transmit a directly modulated 4-PAM data signal and a phase modulated RF clock signal. A receiver sensitivity of −10. 52 dBm was attained for a 20 Gbps 4-PAM VCSEL transmission. The 2 GHz phase modulated RF clock signal introduced a power budget penalty of 0.21 dB. Simultaneous distribution of both data and timing signals over shared infrastructure significantly increases the aggregated data rate at different optical network units within the DCN, without expensive optics investment. We further demonstrate on the design of a software-defined digital signal processing assisted receiver to efficiently recover the transmitted signal without employing costly receiver hardware.

A novel power-efficient high-speed clock management unit using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is one of the most attractive alternatives for complementary metal-oxide semiconductor technology. The QCA widely supports a new paradigm in the field of nanotechnology that has the potential for high density, low power, and high speed. The clock manager is an essential building block in the new microwave and radio frequency integrated circuits. This paper describes a novel QCA-based clock management unit (CMU) that provides innovative clocking capabilities. The proposed CMU is achieved by utilizing edge-triggered D-type flip-flops (D-FFs) in the design of frequency synthesizer and phase splitter. Edge-triggered D-FF structures proposed in this paper have the successful QCA implementation and simulation with the least complexity and power dissipation as compared to earlier structures. The frequency synthesizer is used to generate new clock frequencies from the reference clock frequency based on a combination of power-of-two frequency dividers. The phase splitter is integrated with the frequency synthesizer to generate four clock signals that are 90o out of phase with each other. This paper demonstrates that the proposed QCA CMU structure has a superior performance. Furthermore, the proposed CMU is straightforwardly scalable due to the use of modular component architecture.

A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phaselocked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.

Harmonic fold back reduction at the N‐path filters

SummaryIn this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (fCLK) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the fCLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (fs), and the noise figure of 4.35 dB (using ideal Gm cells) and 6.95 dB (for practical Gm cells). The strongest harmonic folding to the filter pass‐band occurs around 11fs with the attenuation of 23.8 dB. Each Gm cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P1 dB,CP are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.

A low noise clock generator for high-resolution time-to-digital convertors

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.

Half-clock frequency scheme for counter-based digital pulse-width modulator

ABSTRACTA higher reference clock frequency of counter in counter-based digital pulse-width modulator results in a higher quantisation resolution or higher switching frequency. A half-clock frequency scheme and various implementations of double edge-triggered counter are proposed in this article to cut the reference clock frequency and dynamic power consumption in half while maintaining the quantisation resolution and switching frequency unchanged. In other words, the resolution or switching frequency can be doubled with a prime reference clock frequency. Simulation result proves the feasibility of proposed half-clock frequency scheme and its implementations.

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection

An all-digital phase-locked loop with a bang-bang phase-frequency detector (BBPFD) that tracks the optimum loop gain for minimum jitter is proposed. The autocorrelation of the output of BBPFD indicates whether the bang-bang PLL operates in the nonlinear regime or the random noise regime. An adaptive loop gain controller continuously evaluates the autocorrelation of the BBPFD output and adjusts the loop gain to make the autocorrelation zero. The digital loop filter operates at higher than the reference clock frequency to reduce the loop latency and to mitigate the resolution of the digitally controlled oscillator. The prototype chip has been fabricated in a 65-nm CMOS process. The core consumes 5 mW at 2.5 GHz and exhibits root-mean-square jitter of 1.72 ps.