Abstract
A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS.
Highlights
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An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching
An ultra-low phase noise sine-wave generator is used as reference clock of the PLL, since a 40 MHz signal has low slew rates, large amounts of jitter are added at the input stage of the chip, a 640 MHz sine wave is injected and an on-chip divider divides the clock to 40 MHz to feed the PLL as shown in figure 7
Summary
In this design, a traditional charge-pump and phase-frequency detector (PFD) is used to control the PLL. Note that the input of the opamp does not directly use the control signal of the PLL but the voltage across main the capacitor of the loop. A 6-bit DAC is used to set the current of the charge pump to control the loop gain and the bandwidth of the PLL. In both P- and N-MOS side bias points, large decoupling capacitors to ground and supply are added to prevent complete bias disturbance when single-event strikes occur on the bias nodes.
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