Abstract
A low noise 0.8 /spl mu/m CMOS phase locked loop (PLL) with a maximum output frequency of I20 MHz has been developed for a pixel clock generator for a range of computer monitors. Other applications include computer clock generation and disk drives. The synthesizer requires no external components. A low phase noise has been achieved through supply rejection techniques, by placing the oscillator in a high gain feedback loop to minimize its noise contribution, and by dynamically adjusting the PLL bandwidth to maximize the open loop gain. >
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
