Reference Circuit Research Articles

Printed Microstrip Interconnects for Improved RF Performance in mm-Wave Packaging

Printed microstrip interconnects are gaining attention as designers seek a more-compact, lower-loss scheme to replace wire bonds. Aerosol Jet® printed interconnects have the potential to lower insertion losses by creating conductors with arbitrary geometries and zero loop height. Printed dielectric and conductor materials typically have inferior electrical properties compared to bulk-deposited materials. There is a question whether these properties will produce unacceptable S21 losses in printed interconnects. This work presents calculations of the effect of the printed material’s properties on S21. HFSS modeling from 0.1 to 100 GHz was conducted on two representative interconnect structures. A trench in an RF substrate filled with dielectric and a dielectric ramp from a substrate up to a GaAs die. The microstrip (or transmission) line over a filled trench represents the filled region around a die that sits down in a “pocket” in the dielectric and contacts the ground plane. Conductors modeled include a pure copper reference along with conductors with four and ten times the resistivity of bulk silver. The dielectric constant of the insulator varied from 2.8 to 4.3 and the loss tangent varied from 0.004 to 0.04. For simplicity, an unpatterned GaAs die was used in place of an RF IC. The work focuses on estimating any degradations in performance of an ideal reference circuit caused by the material properties of real printed materials. Also presented are the dielectric properties of our current materials along with properties of candidate materials that have better thermo-mechanical properties (shrink, CTE, Tg…).

A high-performance wordline voltage-generating system for low-power low-voltage flash memory

Wordline (WL) voltage-generating system is a crucial block in flash memory. It generates a voltage higher than the supply voltage for reading, programming and erasing in flash memory. However, operation accuracy is deteriorated by the excessive overshoot and ripple voltage. Moreover, current consumption in standby mode shortens the life of memory. The paper presents a high-performance wordline voltage-generating system in 55nm CMOS technology. In active mode, a variable stage and frequency charge pump system is proposed to suppress overshoot and ripple of WL voltage (VWL) when the supply voltage ranges from 1.5V to 2.1V. To cut down standby current, an ultra-low power voltage reference circuit operating in subthreshold region is introduced. When recovering from standby mode, a standby recovery management circuit is utilized to minimize WL voltage setup time. The ripple voltage is 3mV at 30pF load with 20MHz pumping frequency in active mode in post-simulation. The WL voltage setup time when recovery from standby mode is equal to 13.7ns, even though the average standby current is less than 0.98µA typically.

A New Piecewise-Compensated Bandgap Reference Circuit with a Trimming Procedure

A new CMOS bandgap reference (BGR) circuit with a piecewise-compensation circuit and a trimming network is proposed and designed to obtain a bandgap reference voltage with a low-temperature coefficient and a high precision, taking into account the effect of non-ideal factors on the results. The proposed piecewise compensation circuit is designed to achieve a constant reference voltage by using a current mirror to mirror the current, combined with a subtractive circuit and an additive circuit to obtain a low-temperature coefficient over an extensive temperature range. The trim network part is used to change the voltage value of the output reference by controlling the magnitude of the resistance value of the resistors connected to the circuit. The design and simulation of the proposed bandgap reference circuit are obtained by using Cadence Spectre simulation by SMIC 0.18 μm CMOS technology. The results indicates that when the power is 3.3 V and the temperature scope is within -40 °C to 125 °C, the output voltage is 1.2 V with the temperature coefficient equal to 0.658 ppm/°C. When the power varies within 3.2 V to 3.4 V, the linear regulating rate is 0.001019 %/V.

Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight).

A novel bandgap voltage reference based on folding compensation

AbstractThis letter proposes a novel bandgap reference circuit that utilizes both curvature and folding compensation to achieve a temperature coefficient (TC) of 2.23 ppm/°C. Unlike traditional BGRs, the unique folding compensation method of this circuit improves the performance at low temperature and can also be applied within a specific temperature range.

A Novel Ultrafast Turn-Off Failure Detection Method of Integrated Gate Commutated Thyristor for VSC Application

Integrated gate commutated thyristor (IGCT) has prospects in voltage source converter application. However, it has no desaturation characteristic in conducting state like insulated gate bipolar transistor, for which fast turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure detection for blocking converter in deadtime is of great significance. In this letter, an ultrafast IGCT turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure detection method is proposed. First, turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> process and failure mechanism of IGCT is analyzed. It is clarified that turn-off capacitors of gate driver will continue to discharge in turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure, thus generating a voltage drop on turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off mosfet</small> , which can be the criterion of failure. Then prototype, threshold and timing sequence are designed. Analog circuit including amplifier, hysteretic comparator and reference circuit is used for fast and accurate measurement of voltage on <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> . The failure gate current and fall time of turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> trail current is measured in pulse test. Finally, experiments are carried out to verify the feasibility of the proposed scheme. The results show that the proposed scheme can achieve reliable turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</small> failure detection within 19 microseconds. Neither false detection nor missed detection occurred. Proposed method has great accuracy and rapidity, and is convenient in implementation. It will greatly decrease the extreme failure rate of IGCT-based converters.

A high‐efficiency power management unit with wide dynamic range for RF energy harvesting system

AbstractA high‐efficiency power management unit (PMU) with wide dynamic range for radio frequency (RF) energy harvesting system is proposed in this paper. A digital zero current switching (ZCS) and a digital maximum power point tracking (MPPT) circuits are adopted. A sub‐threshold current reference circuit and a subthreshold voltage detection circuit are proposed to reduce the power consumption of always‐on control circuits and improve the conversion efficiency at low input power. A dual‐oscillator is designed to extend the frequency range and widen the input power range with optimized power consumption under low‐end band and high‐end band, respectively. Switch size and on‐time are adjusted according to the input power, which optimizes the conversion efficiency in a wide power range. Proposed PMU is implemented in a standard 180 nm CMOS process. The post‐layout simulation results show that proposed PMU can achieve cold‐start at the input voltage of 280 mV, the power consumption to maintain the PMU is only 9.6 nW. The input power range of the PMU is 11 nW–677 μW. When the input power is 50 nW, a power conversion efficiency (PCE) of 65% is achieved, and the peak PCE can reach 93% at 23.5 μW.

Fault logic circuit design of switching power supply based on soft reference circuit module

The basic idea of the circuit fault diagnosis method based on fault logic is to establish a computer expert database system first, connect the computer to the GPIB interface card, and then connect each intelligent instrument through the GPIB standard bus. Through the connection of the tested object adapter and the tested object, a circuit fault expert diagnosis and test platform are formed. Based on the traditional fault simulation model, this paper improves the fault logic circuit of switching power supply, designs the system model of fault simulation, deals with the logic structure and circuit hierarchy respectively, and produces the final output through the logic gate circuit by comparing the results of the fault logic circuit and the fault-free logic circuit. The designed switching power supply fault logic circuit works in the switching state, which has the characteristics of low loss and high energy conversion efficiency. Through the simulation analysis, the output is connected to the comparator, which plays the role of the whole wave. The simulation results are in line with the parameter indicators. The functional test results of the chip show that the function of the module is basically normal, which has practical application value and good portability and can be used as a reference for similar electrical designs.

Bandgap reference, temperature sensor and low drop-out regulator circuits monolithic sensors in TPSCo 65 nm ISC technology

With Inner Tracking System v3 (ITS3), the ALICE experiment is pursuing a wafer-scale Monolithic Active Pixel Sensor (MAPS). The chip is being developed in TPSCo 65 nm ISC technology which is under study in the framework of CERN EP R&D on monolithic sensors for High Energy Physics (HEP) applications. This contribution presents designs and measurement results of building blocks needed for this chip, in particular bandgap references and temperature sensors. In addition, simulation results of the design of Low Drop-out Regulator (LDO) to be submitted for the next prototyping run will be discussed.

Temperature-Insensitive Ka-Band Transceiver With Ultralow-Noise Self-Calibrated Low Dropout Regulator in 65-nm CMOS

This article proposes a Ka-band transceiver with an integrated local oscillator (LO) generator and multiple low dropout regulators (LDOs) to eliminate the strict requirements to the external power supply network. The proposed self-calibrated LDO eliminates the use of a bandgap reference circuit and its large flicker noise contribution in traditional power regulators to achieve ultralow-noise performance. The output of the proposed LDO is self-calibrated with temperature and process variations by autoconfiguring the feedback coefficient through a digital loop to guarantee the stable performance of its loaded high-speed circuits. The stable gain and output power of the transceiver with temperature variation are achieved by on-chip multiple self-compensation schemes, which include a self-sensing LDO for the power amplifier, a constant- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{\!m}$ </tex-math></inline-formula> bias circuit for the amplification stages, and the temperature-compensated intermediate-frequency amplifiers (TC IFAs) with proportional-to-absolute-temperature (PTAT) gain to further compensate for the gain deviation caused by the second-order effect and large-signal performance difference. Implemented in 65-nm CMOS technology, measurements indicate that the output noise of the proposed LDO is as low as 15 nV/sqrt (Hz) at 10-kHz offset and the integrated power network greatly reduces the noise influence on the LO signal compared with the traditional bandgap-referenced LDO. Furthermore, due to the adoption of the proposed temperature compensation scheme, the small-signal gains of the receiver and transmitter only fluctuate by 1.1 and 1.3 dB from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40\,\,^{\circ }\text{C}$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85~^{\circ }\text{C}$ </tex-math></inline-formula> , respectively, and the output saturated power of the transmitter varies by 0.7 dBm over the entire temperature range.

An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation

This paper presents a simple scheme for a nano-ampere supply and temperature-stabilized current reference based on the well-known Beta multiplier circuit. Under the control of the proposed active resistor temperature coefficient compensation (TCC) circuit, the threshold voltage of the traditional active resistor in the triode region can be reduced and the temperature coefficient (TC) can be adjusted. The proposed current reference circuit was implemented using standard VTH (SVT) MOS devices and included active resistors (MΩ) to achieve area efficiency. The power consumption of the current reference generator designed using a 180 nm CMOS process was 9.2 nW at a supply voltage of 0.55 V. Monte-Carlo simulation results showed that the reference current was 1.96nA, temperature coefficient was 96 ppm/°C over a temperature range of 0–100 °C, and line sensitivity was 0.2 %/V for supply voltages ranging from 0.55 to 1.8 V. The active area was only 0.003 mm2.

Radiation-aware analog circuit design via fully-automated simulation environment

As a result of increased interest in space applications, radiation-aware circuit design has become a major concern to guarantee the safe operation of electronic systems operating under extreme space conditions. As the first step, several ad-hoc simulation approaches have been developed in analog and digital domains to estimate the functional behavior of circuits exposed to high radiation. However, most of these tools are application specific and stand-alone (not integrated into the simulation tools). Also, several commercial CAD solutions exist; however, access to these tools is limited due to security measures. To this end, we have developed a well-equipped, SPICE-integrated, and free-to-access simulation tool, RadiSPICE, capable of running statistical radiation simulations and performing extended temperature and sensitivity analyses. By using RadiSPICE, one can readily predict the functional behavior of circuits after long-term or short-term radiation effects. Moreover, the sensitivity analysis reveals vulnerabilities of the design against radiation and provides valuable design hints to the designer to make circuits radiation-hardened. To demonstrate the proposed tool, we have performed several experiments on two analog building blocks with different topologies (bandgap reference and comparator circuits) using RadiSPICE and discussed the robustness of the designs in detail.

Design of LDO circuit based on curvature compensation reference closed-loop stability

In this paper, a low dropout (LDO) circuit based on a curvature compensation benchmark and closed-loop stability is designed. This circuit compensates for the higher order term of VBE in a BJT through the subthreshold characteristic of MOSFET and achieves the effect of curvature compensation. The bandgap reference circuit provides a stable input voltage for the LDO circuit, while the source follower and adaptive bias circuit improve the response speed and closed-loop stability of the LDO circuit. The temperature drift coefficient of the bandgap circuit is 8.11 ppm/°C, the input voltage is 3–5 V, the output voltage is 2.8 V, and the linear adjustment rate is 0.22%.

A radiation hard bandgap voltage reference for the ARCADIA project

This work presents the design and characterization results of a radiation hard bandgap reference circuit fabricated in a 110 nm CMOS technology for the Main Demonstrator chip of the ARCADIA project. The design, based on a current-mode approach in order to be able to output a smaller than 1.2 V reference voltage, employs diode-connected MOSFETs instead of BJTs to enhance the radiation hardness and a second amplifier to improve the current mirror of the output branch and therefore the line regulation of the circuit. This paper describes the features of the circuit and its measured results.

Novel Methods for Improved Particle Swarm Optimization in Designing the Bandgap Reference Circuit

Novel Methods for Improved Particle Swarm Optimization in Designing the Bandgap Reference Circuit

An LDO Circuit Design Based On On-chip Compensation

This paper proposes a liner low-dropout regulator (LDO) circuit using on-chip steady-state compensation technology. Firstly, a bandgap reference is designed with low temperature drift and low power consumption. Secondly, the on-chip compensation is adopted in the LDO, which can avoid the use of large off-chip capacitors and reduce the layout area of the LDO circuit. The circuit performances are verified in the TSMC 180 nm CMOS process. Test results show that temperature coefficient of the bandgap reference circuit is as low as 4.3 × 10-6 °C in the temperature range of -40°C to 125°C. The static current under the 3V power supply voltage is 4 μA. The LDO output voltage Vout is 1.8V . And the core area of the chip is 0.0848 mm2.

A 0.5–1.7 V Efficient and PVT-Invariant Constant Subthreshold gm Reference Circuit in CMOS

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{S}$ </tex-math></inline-formula> , while consuming 1.95 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> .

A Sub-1-V 8.5-ppm/°C Sampled Bandgap Voltage Reference

This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled onto a capacitor. By sampling the voltages onto a capacitor, we eliminate the need for an opamp in the bandgap core, which tends to be the dominant source of noise and offset concerns in low voltage bandgap designs in scaled technologies. A prototype was designed and fabricated in 28nm TSMC HPC+ technology with a nominal output voltage of 108mV. It demonstrates a temperature coefficient of 8.5ppm/°C between −40°C and 125°C, and occupies an area of 0.0075mm2 while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.6\mu \text{W}$ </tex-math></inline-formula> of power.

A fully-integrated all-MOS 1.2 V low-dropout regulator for ultra-low power applications

This paper presents a fully-integrated all-MOS low-dropout regulator (LDO) with ultra-low power (ULP) consumption. The proposed design uses the threshold voltage difference (ΔVth) based references to generate the minimize load bias generation circuit, and all-MOS current and voltage reference circuits, which reduces both area and power consumption. On the ultra-low bias current condition, error amplifier (EA) is designed working in the subthreshold region to increase DC gain and programmable current reference is applied to enhance the transient response. The proposed prototype occupies 0.03 mm2 area including compensation and decouple cap in SMIC 55 nm CMOS technology. The measurement result shows that the ultra-low quiescent current of 10 samples can be as low as 44.7 nA. And for a battery supply (Vin) of 1.8–3.6 V, a regulated VOUT is attained with a line/load regulation of 9.5 mV/V and 0.81 mV/mA respectively. The experiment results indicate that the undershoot/overshoot is 50.4 mV and 25.5 mV respectively when the load current is varied from 0 to 1 mA within 100 ns under the load of 1 nF load capacitor.

A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS

In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.