A fully-integrated all-MOS 1.2 V low-dropout regulator for ultra-low power applications

Abstract

This paper presents a fully-integrated all-MOS low-dropout regulator (LDO) with ultra-low power (ULP) consumption. The proposed design uses the threshold voltage difference (ΔVth) based references to generate the minimize load bias generation circuit, and all-MOS current and voltage reference circuits, which reduces both area and power consumption. On the ultra-low bias current condition, error amplifier (EA) is designed working in the subthreshold region to increase DC gain and programmable current reference is applied to enhance the transient response. The proposed prototype occupies 0.03 mm2 area including compensation and decouple cap in SMIC 55 nm CMOS technology. The measurement result shows that the ultra-low quiescent current of 10 samples can be as low as 44.7 nA. And for a battery supply (Vin) of 1.8–3.6 V, a regulated VOUT is attained with a line/load regulation of 9.5 mV/V and 0.81 mV/mA respectively. The experiment results indicate that the undershoot/overshoot is 50.4 mV and 25.5 mV respectively when the load current is varied from 0 to 1 mA within 100 ns under the load of 1 nF load capacitor.