Reference Circuit Research Articles

Curvature-Compensated Bandgap Voltage Reference with Low Temperature Coefficient

Resistance errors in bandgap reference (BGR) circuits often cause deviations in design indicators, and it is true that utilizing various compensation techniques mitigates the impact of resistance errors. In this paper, an original BGR circuit with 180 nm BCD processing is presented, which uses an improved high-order compensation and curvature compensation. The proposed BGR contains four main blocks, including a start-up stage, a first-order temperature compensation stage, a high-order temperature compensation stage, and a curvature compensation stage. Meanwhile, a trimming resistor array structure is designed to revise the temperature coefficient (TC) deviation of the test output voltage from the theoretical design value. Through wafer-level laser trimming technology, the measurement results are achieved with very little difference from the theoretical design value. The proposed BGR provides a stable reference voltage at 1.25 V with a low TC and strong power supply rejection (PSR). Within temperatures ranging from −45 °C to 125 °C, the measured TC shows an optimal value at 4.2 ppm/°C and the measured PSR shows −100 dB.

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

Design of Area-Optimized Low-power Voltage Reference Circuits using a Modified Particle Swarm Optimization

A Sub-1 ppm/°C Reference Voltage Source with a Wide Input Range

With the continuous advancement of electronic technology, the application of high-voltage integrated circuits is becoming increasingly prevalent in fields such as power systems, medical devices, and industrial automation. The reference circuit within high-voltage integrated circuits must not only exhibit insensitivity to temperature variations but also maintain stability across a broad voltage supply. This paper presents a bandgap reference (BGR) source capable of operating over a wide input range. This BGR employs a high-order curvature compensation method to eliminate nonlinear voltage terms, resulting in minimal temperature drift. The circuit achieves an impressive temperature coefficient (TC) of 0.88 ppm/°C over a temperature range from −40 °C to 130 °C. To ensure stable operation within a 4–40 V range, the design incorporates a pre-regulation circuit that stabilizes the supply voltage of the BGR core at a fixed value, thereby enhancing the ability to withstand variations in power supply voltage.

A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation

In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native VTH, medium VTH) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.

An Energy‐Efficient Fully On‐Chip CMOS Temperature Sensor for Portable Applications With an RFoM of 2.79 pJ.K2

ABSTRACTThis article describes an energy‐efficient, low‐power CMOS temperature sensor suitable for portable applications. The sensor's front‐end circuitry is designed with a reference voltage (V), complementary to absolute temperature (CTAT) voltage (V), and ramp voltage generators. The ramp voltage (V) is produced by utilizing a current reference circuit. The ramp voltage is compared with independent and temperature‐dependent voltages to perform the voltage‐to‐frequency conversion. Conversion from frequency to digital output is achieved through an asynchronous counter with an on‐chip oscillator. The proposed design is realized in a 0.18‐m CMOS technology and attains a power usage of 604.4 nW at 27°C with an operating voltage of 0.5 V. Furthermore, it obtains an inaccuracy of +0.71/−0.73°C over −40°C to 125°C temperature range with an active area of 0.025 mm2. Moreover, the designed sensor circuit offers a resolution of 0.17°C with an energy conversion of 96.7 pJ.

A High Sensitivity CMUT-Based Passive Cavitation Detector for Monitoring Microbubble Dynamics During Focused Ultrasound Interventions.

Tracking and controlling microbubble (MB) dynamics in the human brain through acoustic emission (AE) monitoring during transcranial focused ultrasound (tFUS) therapy are critical for attaining safe and effective treatments. The low-amplitude MB emissions have harmonic and ultra-harmonic components, necessitating a broad bandwidth and low-noise system for monitoring transcranial MB activity. Capacitive micromachined ultrasonic transducers (CMUTs) offer high sensitivity and low noise over a broad bandwidth, especially when they are tightly integrated with electronics, making them a good candidate technology for monitoring the MB activity through human skull. In this study, we designed a 16-channel analog front-end (AFE) electronics with a low-noise transimpedance amplifier (TIA), a band-gap reference circuit, and an output buffer stage. To assess AFE performance and ability to detect MB AE, we combined it with a commercial CMUT array. The integrated system has 12.3 - [Formula: see text] receive sensitivity with 0.085 - [Formula: see text] minimum detectable pressure (MDP) up to 3 MHz for a single element CMUT with 3.78 [Formula: see text] area. Experiments with free MBs in a microfluidic channel demonstrate that our system is able to capture key spectral components of MBs' harmonics when sonicated at clinically relevant frequencies (0.5 MHz) and pressures (250 kPa). Together our results demonstrate that the proposed CMUT system can support the development of novel passive cavitation detectors (PCD) to track MB activity for attaining safe and effective focused ultrasound (FUS) treatments.

A 3216 μm2 MOS-Based Temperature Sensor with a Wide Temperature Measurement Range and Linear Readout

This paper introduces an MOS-based intelligent temperature sensor with a linear readout. Compared with similar designs, the proposed sensor utilizes the DIBL effect to reduce the precision requirement for the voltage reference source and compensate for the temperature measurement range. A compact voltage reference circuit is introduced, which generates two reference voltage bases using only three transistors. In addition, the proposed digital readout circuit does not require a subtractor or a divider, further saving area. Fabricated in a 55 nm CMOS process, the proposed sensor occupies a compact area of 3216 μm2. Post-simulation results show it has a maximum error of −0.52/+0.28 °C within the temperature range of −20 °C to 120 °C after two-point calibration. The power supply voltage range of the sensor is 0.8 to 1.8 V. It has a maximum voltage sensitivity of 5.7 °C/V and its power consumption is only 166 nW, with a power supply voltage of 0.8 V.

A Low-temperature drift bandgap reference circuit with startup enhancement and high currents driving

A Low-temperature drift bandgap reference circuit with startup enhancement and high currents driving

A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of −55 to 100 °C without using amplifiers and resistors

The paper presents a 0.5 V, ultra-low power current, and voltage reference circuit in a single block, giving reference values of 90.7 pA and 288 mV. The proposed block uses proper addition of CTAT and PTAT curves, resulting in an excellent temperature coefficient of 15.2 ppm/°C and 36.8 ppm/°C for compensated current and voltage values, respectively, at a nominal supply of 0.5 V for a wide temperature range of −55 °C to 100 °C. Usage of gate leakage transistors in place of resistors helps in reducing the power and area of the circuit to 0.087 mm2. The circuit is implemented in 90 nm technology and operates effectively across a wide voltage range of 0.5 V–2.6 V with a supply sensitivity of 0.028 %/V and 0.154 %/V for current and voltage reference, respectively. The entire circuit takes a power of 275.26 pW at nominal conditions.

Segment-compensated Bandgap Reference Generator with Low-temperature Drift

Abstract In this paper, a segment-compensated low-temperature-drift bandgap reference generator is proposed and designed to get the high-order nonlinear temperature characteristics for the bandgap reference circuit. Based on the Nuvoton 0.35 μm BCD process, the circuit is simulated and analyzed. The result is that a temperature coefficient of 1.12 ppm/℃ over the range of -40℃ to 125℃ is obtained, which is much lower than the 6.88 ppm/℃ before compensation. It is demonstrated that the power supply rejection ratio is 141.3 dB at 1, 000 HZ, low-frequency open-loop gain is 75 dB, and a phase margin is 57°.

A high‐precision voltage reference with a curvature‐compensated bandgap for fluorescence detection

SummaryFluorescent optical fiber temperature sensors require accurate online temperature monitoring in hazardous environments with strong electromagnetic fields, high voltages, flammability, or explosiveness. This imposes stringent requirements on the temperature coefficient stability of the bandgap reference (BGR) circuit. To address these challenges, this paper proposes a high‐order curvature compensation bandgap reference (HCC_BGR) circuit fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS (BCD) process. A traditional first‐order bandgap reference (TRA_BGR) circuit is also fabricated for comparison. Experimental results demonstrate that the proposed HCC_BGR circuit generates a stable 1.22‐V reference voltage with a low‐temperature coefficient of 5.56 ppm/°C from −20°C to 85°C. Compared to the TRA_BGR circuit, the HCC_BGR reduces the temperature coefficient by 3.07 times. Furthermore, the low‐dropout regulator (LDO) using the proposed HCC_BGR exhibits excellent line sensitivity of 1.52%/V from 3.4 to 5 V.

A Two-Stage Sub-Threshold Voltage Reference Generator Using Body Bias Curvature Compensation for Improved Temperature Coefficient

Leakage diodes cause deviations in the thermal drift of ultra-low-power two-transistor (2T) reference circuits, resulting in either convex or concave output voltages against temperature, depending on the reference transistor types (n-type/p-type). This paper investigates the combined application of the convexity and concavity properties exhibited by the output voltage of complementary 2T references, one n-type and one p-type. By exploiting the body bias effect, this approach mitigates variations in the output reference voltage caused by temperature fluctuations. Software optimization is also used to obtain the required aspect ratios after formulating the required criteria for drain-induced barrier lowering (DIBL) elimination in the first stage. The performance of the proposed reference is evaluated by post-layout Monte Carlo simulations. In the range of 0 °C to 100 °C, the output reference voltage has an average temperature coefficient (TC) of 26.7 ppm/°C without any temperature trim. The output reference voltage is 195.5 mV with a standard deviation of 13.6 mV. The line sensitivity (LS) is 17.1 ppm/V in the supply voltage range of 0.5 V to 2.1 V at 25 °C. At 25 °C and 0.5 V, the power consumption is 28.8 pW, increasing to a maximum of 1.3 nW at 100 °C and 2.1 V.

Low power consumption and fast response of low dropout regulator design

A low power consumption and fast response low voltage difference linear regulator circuit is designed for on-chip SOC circuit to achieve low power consumption, fast response, and high stability. The internal design mainly includes a low power bandgap reference circuit, a light and heavy load detection circuit, and a transient enhancement circuit. The circuit is designed with 0.35 μm BCD technology, and the layout design is completed. The VIN is from 2.5 V to 5 V, the VOUT from 2.5 V to 3.3 V, and the maximum load is 250 mA. The simulation results show that the static current is 2.6 μA at normal temperature with no load. When the load jumps, the overshoot is 44 mV and the recovery time is 52 μs, meeting the design requirements of low power consumption and fast response.

A 10.5 ppm/°C Modified Sub-1 V Bandgap in 28 nm CMOS Technology with Only Two Operating Points

Reference voltage/current generation is essential to the Analog circuit design. There have been several ways to generate quality reference voltage using bandgap reference (BGR) and there are mainly two types: current mode and voltage mode. The current-mode bandgap reference (CBGR) is widely accepted in industry due to having an output voltage which is below 1 V. However, its drawbacks include a lack of proportional to absolute temperature (PTAT) current availability, a large silicon area, multiple operating points, and a large temperature coefficient (TC). In this paper, various operating points are explained in detail with diagrams. Similar to the conventional voltage mode bandgap reference (VBGR) circuits, modifications of the existing circuits with only two operating points have also been proposed. Moreover, the proposed BGR occupies a much smaller area due to eliminating the complimentary to absolute temperature (CTAT) current-generating resistor. A new self-biased opamp was introduced to operate from a 1.05 V supply, reducing systematic offset and TC of the BGR. The proposed solution has been implemented in 28 nm CMOS TSMC technology, and extraction simulations were performed to prove the robustness of the proposed circuit. The targeted mean BGR output is 500 mV, and across the industrial temperature range (−40 to 125 °C), the simulated TC is approximately 10.5 ppm/°C. The integrated output noise within the observable frequency band is 19.6 µV (rms). A 200-point Monte Carlo simulation displays a histogram with a 2.6 mV accuracy of 1.2% (±3-sigma). The proposed BGR circuit consumes 32.8 µW of power from a 1.05 V supply in a fast process and hot (125 °C) corner. It occupies a silicon area of 81 × 42 µm (including capacitors). This design can aim for use in biomedical and sensor applications.

A 0.6 V voltage reference circuit with 57 ppm/°C temperature coefficient, 73 KΩ output impedance and 0.080%/V line sensitivity for energy efficient applications

In this paper, a voltage reference circuit generating 0.6 V developed in the Semiconductor Laboratory (SCL) 0.18 μm standard CMOS technology has been presented. It is based on the principle of Beta multiplier circuit. Operating under a supply voltage of 1.8V, the proposed reference accomplishes a line sensitivity as low as 0.080%/V across a voltage range of 1.8 V to 3.5 V. In addition to a low line sensitivity, it achieves a low temperature coefficient of 57 ppm/ °C over the temperature range of −40 °C to +85 °C. The circuit furnishes a power supply rejection ratio (PSRR) of −75.72 dB. The improved load regulation feature allows the circuit to drive loads as low as 73 KΩ with minimum variation. A reliable nature of the circuit has been observed on examining the response for different process corners and variations.

An approach for designing leakage compensated voltage reference circuit

ABSTRACT In this paper, the design of CMOS-based and recyclic folded cascode (RFC)-based voltage reference circuits is presented. Further inherent leakage compensation technique using diode connected MOSFET is introduced, which results in the compensation of high-temperature leakage current and a reduction in consumed power. Moreover, current mirror-induced mismatch and supply dependency reduces. Furthermore, temperature range and power supply rejection ratio (PSRR) improves. Later, comparison between the two configurations, i.e. with and without leakage compensation, has been presented. The minimum value of the achieved temperature coefficient on applying leakage compensation is 4.2 ppm/ºC for the proposed RFC op-amp-based voltage reference circuit with improved temperature range by 40°C. The obtained value of PSRR is −88.2 dB at 10 Hz, −66.8 dB for 1 KHz and −61.6 dB for 1 MHz frequency, with the line sensitivity of 0.031%/V and the variation of 1.69 mV for an entire operating temperature range. All the simulation results are obtained at 0.7 V supply voltage in 180 nm SCL technology.

Explosive Growth of Image Sensors in Smart Government Technology and Economic Scale

CMOS image sensor is a rapidly developing image sensor product in the past decade. Relying on the advantages of process compatibility with standard CMOS process, CMOS image sensor integrates analog photoelectric photosensitive circuit and digital signal processing circuit to become a small and powerful system on chip. This article mainly studies the explosive growth of image sensors in smart government technology and economic scale. The main purpose of this article is to study the technical application of image sensors, reduce the administrative cost of social governance, improve the level of government governance, benefit the public, and realize the requirements of smart government affairs and rapid economic development of the city. This study tested the static performance of the analog-to-digital conversion circuit by inputting a limited number of sampling points, and its integral nonlinearity and differential nonlinearity were both less than 1LSB. The bandgap reference circuit provides a reference level for the entire system. It uses two PNP-type bipolar transistors parasitic in the CMOS process to achieve a temperature and voltage-independent bandgap reference voltage through the feedback of the operational amplifier. It is ideal for use In the case of resistance simulation, its accuracy reaches 16.6ppm. The scanning method of the pixel array uses multi-sampling technology to increase the dynamic range of the sensor by 2N times. The correlated sub-sampling technology eliminates the fixed pattern noise between pixel units. The use of pipelined analog-to-digital converters can achieve good resolution, speed and area compromise.Through the realization and simulation of transistor-level circuits, the performance of each part of the system meets the requirements of design and application.

Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars

Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range

Hardware Trojan Detection using Graph Neural Networks

The globalization of the Integrated Circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted third party entities around the world. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, and deny the functionality of the intended design. Various HT detection methods have been proposed in the literature; however, many fall short due to their reliance on a golden reference circuit, a limited detection scope, the need for manual code review, or the inability to scale with large modern designs. We propose a novel golden reference-free HT detection method for both Register Transfer Level (RTL) and gate-level netlists by leveraging Graph Neural Networks (GNNs) to learn the behavior of the circuit through a Data Flow Graph (DFG) representation of the hardware design. We evaluate our model on a custom dataset by expanding the Trusthub HT benchmarks trusthub1. The results demonstrate that our approach detects unknown HTs with 97% recall (true positive rate) very fast in 21.1ms for RTL and 84% recall in 13.42s for Gate-Level Netlist.