Reference Circuit Research Articles

High-PSRR Wide-Range Supply-Independent CMOS Voltage Reference for Retinal Prosthetic Systems

This paper presents a fully integrated voltage-reference circuit for implantable devices such as retinal implants. The recently developed retinal prostheses require a stable supply voltage to drive a high-density stimulator array. Accordingly, a voltage-reference circuit plays a critical role in generating a constant reference voltage, which is provided to a low-voltage-drop regulator (LDO), and filtering out the AC ripples in a power-supply rail after rectification. For this purpose, we use a beta-multiplier voltage-reference architecture to which a nonlinear current sink circuit is added, to improve the supply-independent performance drastically. The proposed reference circuit is fabricated using the standard 0.35 µm technology, along with an LDO that adopts an output ringing compensation circuit. The novel reference circuit generates a reference voltage of 1.37 V with a line regulation of 3.45 mV/V and maximum power-supply rejection ratio (PSRR) of −93 dB.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

Low Power Fast Settling Switched Capacitor PTAT Current Reference Circuit for Low Frequency Applications

Low Power Fast Settling Switched Capacitor PTAT Current Reference Circuit for Low Frequency Applications

A comparison study on electromagnetic susceptibility of current reference circuits with scaling-down technologies and schemes

This paper studies the effects of process node and circuit schemes on the electromagnetic susceptibility (EMS) of current reference circuits. Three reference circuits using PDSOI with technology node of 0.5 μm (VREF50), 0.35 μm (VREF33) and 0.18 μm (VREF18) are used. VREF50 has an additional CASCODE structure to achieve a PSRR enhancement. The test results show that when the electromagnetic interference (EMI)is injected into the terminals VDD and VSS, the reference currents in both of the three circuits exhibit a negative shift. The main reason is that the drain voltage of the transistor close to the terminal VDD fluctuates greatly, causing a deviation from the saturation to the linear region from time to time, hence reducing the average value of the current. The higher voltage margin with the large process node, the stronger the immunity of the reference circuit to EMI. It is worth noting that the CASCODE structure has a negative effect on low frequency large-signal EMI. Therefore, VREF50 and VREF33 have the similar EMS. In a higher frequency range, the parasitic effect brought by the CASCODE structure becomes more serious, which increases the high-frequency impedance of the circuit. Finally, simulation results imply that the immunity level is improved by decreasing bypass capacitor between the sensitive node and the VDD to reduce the EMI injection, and replacing the nonlinear device by a positive temperature coefficient resistor to improve the circuit linearity.

A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply

This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from -40°C to 125°C, 0.15% line regulation, and draws 7.2μ\textA from a 1.05V supply.

Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design

In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU.Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chainsstructure.In this paper two new hybrid full adders have been proposedwith an aim to achieve low PDP.Further the paper proposesripple carry adder (RCA) in chainstructure using triplet design approach to improve the driving strength. Fivedifferent hybrid full adders topologies have been implementedto build 4-bit RCA adder in regular and triplet logic design and PDP improvement is obtained in triplet design approach. All the simulations are done on 45nm technology and performance analysis done over the voltage range 0.6 V to 1.2V in Cadence Virtuoso simulation software. Simulation results are obtained to show that delay and PDP has improved in triplet designing and the proposed hybrid adders represents least PDP among other implemented reference circuits.

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

In this paper, a low‐noise amplifier (LNA) with process, voltage, and temperature (PVT) compensation for low power dissipation applications is designed. When supply voltage and LNA bias are close to the subthreshold, voltage has significant impact on power reduction. At this voltage level, the gain is reduced and various circuit parameters become highly sensitive to PVT variations. In the proposed LNA circuit, in order to enhance efficiency at low supply voltage, the cascade technique with gm boosting is used. To improve circuit performance when in the subthreshold area, the forward body bias technique is used. Also, a new PVT compensator is suggested to reduce sensitivity of different circuit's parameters to PVT changes. The suggested PVT compensator employs a current reference circuit with constant output regarding temperature and voltage variations. This circuit produces a constant current by subtracting two proportional to absolute temperature currents. At a supply voltage of 0.35 V, the total power consumption is 585 μW. In different process corners, in the proposed LNA with PVT compensator, gain and noise figure (NF) variations are reduced 10.3 and 4.6 times, respectively, compared to a conventional LNA with constant bias. With a 20% deviation in the supply voltage, the gain and noise NF variations decrease 6.5 and 34 times, respectively.

Cryogenic Bandgap Reference Circuit With Compact Model Parameter Extraction of MOSFETs and BJTs for HPGe Detectors

This article presents the development of a cryogenic bandgap reference (BGR) circuit in a standard 0.18-μm CMOS process for high-purity germanium (HPGe) detectors for low-background physics experiments. It provides a temperature-independent reference for mixed-signal circuits such as a ramp generator. A reliable cryogenic model is essential for the circuit design. The parameters of metal-oxide-semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs) were characterized and extracted at cryogenic temperatures from dc measurements on various geometries. MOSFETs had a general increase in threshold voltage and carrier mobility, a decrease in subthreshold slope at 77 K, with respect to 300 K. A new set of compact model parameters for MOSFETs and BJTs under cryogenic temperatures have been extracted. The relative errors between simulation and measurement were below 10% in almost all the bias regions for various device dimensions at 77 K. Two different BGR circuits were designed with the modified compact model parameters and evaluated from 77 K to 300 K. Temperature coefficient of less than 0.2 mV/K has been achieved over the whole range from 300 K to 77 K.

Automation of Bandwidth Re-design and its Applications in Amplifier Tuned Oscillators Based on Nullors

In this paper, the method for the design automation of a narrow band-pass amplifier, and hence the amplifier tuned oscillator is discussed. A fixator approach is utilized in this method to design the narrow band-pass amplifiers and a reference circuit is required for this process. The fixator–norator pair helps to generate an extra sub-circuit, generally the feedback network; the addition of this sub-circuit in the actual amplifier circuit will modify the frequency response of the amplifier. The amplifier now behaves like an active narrow band-pass filter, which exactly follows the frequency response of the model circuit. This can be turned into an oscillator by providing positive feedback. Such a circuit possesses independent frequency and amplitude control. Hence, the re-designed circuit can be employed as an active filter or an oscillator at the selected center frequency. In addition to the technical merits, the proposed method has pedagogical importance. Few case studies are worked out in this paper to demonstrate the method.

1V relaxation oscillator with integrated voltage and current reference

This Letter presents a novel relaxation oscillator with integrated voltage and current reference circuit, which generates a 32 kHz clock reference with 1% accuracy and has total power consumption of 122 nW at 1 V. Its temperature coefficient (TC) is 104 ppm/°C with a temperature range of -40 to 100°C, and its supply voltage accuracy is 1.6%/V from 1 to 1.8 V. The proposed oscillator uses the voltage reference directly to compare with the charging capacitor voltage, and the charging current is derived from the voltage reference divided by one temperature-independent resistor. The advantages are that the accuracy of output frequency and TC can be trimmed simultaneously and independently. It is fabricated in 0.18 μm CMOS technology and occupies 0.059 mm 2 including the voltage and current reference circuits.

A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within −40 °C to 120 °C

This paper presents a switched capacitor network (SCN)-based bandgap voltage reference (BGR) circuit designed and implemented in a 65nm standard CMOS process with a wide temperature range, high precision, low supply voltage and low power consumption for IoT device application. The proposed BGR employs a 2x charge pump with ripple optimization design to supply the ${V} _{\mathbf {EB}}$ generator, which can relax ${V} _{\mathbf {DD}}$ from 0.9V to 0.5V.A proportional to absolute temperature (PTAT) current source is proposed to bias the PNP BJT in order to reduce the nonlinearity of ${V} _{\mathbf {EB}}$ . Moreover, a voltage divider SCN with low leakage consideration to form the complementary to absolute temperature (CTAT) voltage is designed to reduce the nonlinearity of its coefficient, while a series-parallel SCN with adjusted clock swing to form the PTAT voltage is designed to improve the line regulation of the BGR. The measurement result shows that the proposed BGR has a temperature coefficient (TC) of 42 ppm/°C at 0.5V supply within −40 °C to 120 °C. The line regulation is 3.2mV/V or 0.64%/V from 0.5V to 1V. Based on 6-chip test result, it shows a $3\sigma / \mu $ variation of 3.08% before trimming, while 0.36% after trimming.

Compact Current Reference Circuits with Low Temperature Drift and High Compliance Voltage.

Highly accurate and stable current references are especially required for resistive-sensor conditioning. The solutions typically adopted in using resistors and op-amps/transistors display performance mainly limited by resistors accuracy and active components non-linearities. In this work, excellent characteristics of LT199x selectable gain amplifiers are exploited to precisely divide an input current. Supplied with a 100 µA reference IC, the divider is able to exactly source either a ~1 µA or a ~0.1 µA current. Moreover, the proposed solution allows to generate a different value for the output current by modifying only some connections without requiring the use of additional components. Experimental results show that the compliance voltage of the generator is close to the power supply limits, with an equivalent output resistance of about 100 GΩ, while the thermal coefficient is less than 10 ppm/°C between 10 and 40 °C. Circuit architecture also guarantees physical separation of current carrying electrodes from voltage sensing ones, thus simplifying front-end sensor-interface circuitry. Emulating a resistive-sensor in the 10 kΩ–100 MΩ range, an excellent linearity is found with a relative error within ±0.1% after a preliminary calibration procedure. Further advantage is that compliance voltage can be opposite in sign of that obtained with a passive component; therefore, the system is also suitable for conditioning active sensors.

Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity

Based on three groups of different offset voltages, a bandgap reference (BGR) and power-ON reset (POR) hybrid circuit is implemented in 65-nm CMOS. The BGR using amplifier offset voltage and current matching, and the POR using offset voltage comparison and loop settling feature, respectively, are proposed. This circuit, with low-quiescent current, not only generates a stable reference voltage independent of voltage and temperature variations, but also provides a high-robust supply-ramp-rate-tolerant power-ON/brown-out reset signal with a hysteretic window of 18–24 mV. Experimental results show that the circuit with line regulations (LNRs) of 2.63%–4.28%/V and temperature coefficients (TCs) of 22–32 ppm/°C across multiple chips has a power dissipation around $2.25~\mu \text{W}$ from a 1-V supply voltage. The circuit achieves a low noise density of 18.5 nV/ $\surd $ Hz at 100-Hz offset frequency and a good figure of merit (FoM) performance. With an active core area of 0.014 mm2, the circuit has fixed reset trip voltages under the supply ramp time of 0.4–100 ms.

A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference

This study proposes an output capacitor-less linear regulator with high power supply rejection (PSR) for a wireless power transmission system. To achieve high PSR with a noisy input voltage, a fully integrated linear regulator with its reference circuit supplied by the output voltage is proposed. The proposed technique can isolate the reference circuit from the noisy $\text{V}_{IN}$ , thereby reducing the requirements of the conventional bulky low-pass filter loading the reference voltage node while achieving superior PSR performance. The regulator uses an N-type pass transistor and a dual-feedback structure to achieve wideband ripple-filtering and fast transient responses. The proposed regulator is compatible with typical biomedical implants requiring a 10mA load current at 1.1V output voltage while consuming a total quiescent current of $276~\mu $ A. A PSR performance was measured to be −48 and −56 dB against the $\text{V}_{IN}$ and charge pump at 10 MHz, respectively. The unity gain bandwidth (UGB) of the regulator was 291MHz. The proposed regulator was fabricated using commercial TSMC 0.18- $\mu \text{m}$ CMOS technology with an area of 0.1054 mm2 including the reference circuit.

Implementation of a Pharmacokinetic Model for Inhaled Anesthetics Into a Software-Based Anesthesia Workstation for LLEAP-Compatible Simulators.

Laerdal Learning Application (LLEAP)-compatible simulation manikins lack some specific functions that can be useful in anesthesia simulation scenarios. Our objective was to develop a software-based anesthesia workstation with a pharmacokinetic model for inhaled anesthetics for this simulation platform. A Windows Presentation Foundation application that emulates an Aespire anesthesia workstation was created. The Gas Man simulator (Med Man Simulations) was used as a reference for the pharmacokinetic model. A concordance analysis was made between the results obtained by our model and the reference, in open and semiclosed circuit, in both 70- and 140-kg patients. The mean of the differences between the compartments was less than 0.01 vol% in all circumstances. The percentile rank P2.5 to P97.5 was less than 0.5 vol% in all compartments, except for the open circuit compartment. No significant differences were found between both pharmacokinetic models. We consider that our software-based anesthesia workstation can be useful for simulating mechanical ventilation and halogenated administration in different scenarios.

0.7-V supply, 21-nW All–MOS voltage reference using a MOS-Only current-driven reference core in digital CMOS

A nano-power all-MOS voltage reference circuit is proposed without any integrated resistor or bipolar transistor to generate multiple voltage sources in inexpensive digital CMOS technologies. The design is based on a current-driven voltage reference core made by standard nMOS transistors only, and can be powered up by a flexible biasing current with no consideration on its temperature characteristics. The sensitive core is shielded from the unregulated voltage supply via a voltage follower MOS transistor, whose gate terminal is driven by a supply-insensitive voltage source coming from the internal biasing configuration. The additional voltage reference is generated using the type of the biasing current made by the main voltage reference loaded by a transistor. A MOS-only implementation of the proposed reference employs MOS devices instead of passive resistors and linear capacitors. A prototype of the proposed solution consumes 30 ​nA with an area of 0.01 ​mm2 in 0.18-μm CMOS process, producing a main voltage reference of 147 ​mV while operating at the supply voltage down to 0.7 ​V. Simulation results demonstrate an average temperature coefficient (TC) of 66.38 ​ppm/°C for a temperature range of −40 to 120 ​°C. The line sensitivity is about 0.031%/V for the line voltages above 1.3 ​V. The mean power supply rejection ratio (PSRR) is −90 dB and −64.4 ​dB ​at 10 ​Hz and 1 ​MHz, respectively, when the voltage supply is set to 1.8 ​V and an equivalent MOS capacitor of 5 ​pF is used at the output. The 1% start-up settling time is 240 μs for a 1.0 ​V voltage supply step, and can be reduced by increasing the supply voltage magnitude.

Wide-Supply-Voltage-Range CMOS Bandgap Reference for In Vivo Wireless Power Telemetry

The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35-μm SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV/V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of −54 dB, and temperature coefficient of 11.9 ppm/°C in the temperature range of 25 to 100 °C.

A tunable low noise high PSRR high accuracy bandgap reference using stacked-long cascode technique in 14 ​nm FinFET process

A tunable CMOS bandgap reference circuit is presented. To improve the match performance of the current mirror, the proposed bandgap is realized with stacked-long Cascode technique. A detailed analysis of various error sources is provided and the techniques to reduce them are discussed. The bandgap reference with an accuracy of ±1.2% from −40 ​°C to 125 ​°C draws 57μA from a 1.8 ​V supply, and occupied 0.0036 ​mm2 in a 14 ​nm FinFET Process. The output noise is 0.76μV (rms) and the PSRR is −115dB@DC.

A 0.7 V 5 nW CMOS sub-bandgap voltage reference without resistors

A 0.7 V 5 nW CMOS Sub-Bandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementary-to-absolute-temperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and sub-threshold transistors. The sub-Bandgap voltage reference is implemented in a 0.18-µm CMOS process. Measured results show that the reference can run with 0.7 V supply voltage, while the power consumption is only 5 nW at room temperature, the area is 0.026 mm2 and the PSRR of better than − 48 dB over the full frequency range is achieved. The average temperature coefficient is 49 ppm/°C with a temperature range of − 40 to 125 °C. Also the line sensitivity is 0.02%/V.

Voltage Reference With Linear-Temperature-Dependent Power Consumption

This article presents a novel pico-watt voltage reference (VR) circuit whose power consumption is well controlled at high temperature. Unlike a traditional pico-watt VR circuit whose power consumption increases exponentially with temperature, the power consumption in this article increases linearly with temperature, thus saving much energy at high temperature. It generates the reference voltage through a 2-transistor (2-T) structure and a current generator to well control the current versus temperature. In the current generator, a gate leakage transistor replaces a huge resistor, thus saving 4-mm2 area. Fabricated in a 0.13- $\mu \text{m}$ CMOS process, this VR circuit generates a reference voltage of about 560 mV and shows an average temperature coefficient (TC) of 18.4 ppm/°C after trimming across −25 °C to 85 °C and a line sensitivity (LS) of 0.15%/V, while consuming 20 pW at 1-V ${V} _{\text {DD}}$ and 27 °C. The power consumption at 3.3-V ${V} _{\text {DD}}$ and 85 °C is 114 pW, which is at least two times smaller than reported in state-of-the-art work at high temperature. The core area is 0.003 mm2.