An approach for designing leakage compensated voltage reference circuit

Abstract

ABSTRACT In this paper, the design of CMOS-based and recyclic folded cascode (RFC)-based voltage reference circuits is presented. Further inherent leakage compensation technique using diode connected MOSFET is introduced, which results in the compensation of high-temperature leakage current and a reduction in consumed power. Moreover, current mirror-induced mismatch and supply dependency reduces. Furthermore, temperature range and power supply rejection ratio (PSRR) improves. Later, comparison between the two configurations, i.e. with and without leakage compensation, has been presented. The minimum value of the achieved temperature coefficient on applying leakage compensation is 4.2 ppm/ºC for the proposed RFC op-amp-based voltage reference circuit with improved temperature range by 40°C. The obtained value of PSRR is −88.2 dB at 10 Hz, −66.8 dB for 1 KHz and −61.6 dB for 1 MHz frequency, with the line sensitivity of 0.031%/V and the variation of 1.69 mV for an entire operating temperature range. All the simulation results are obtained at 0.7 V supply voltage in 180 nm SCL technology.