Redundant Bits Research Articles

Bit Reduction for Locality-Sensitive Hashing.

Locality-sensitive hashing (LSH) has gained ever-increasing popularity in similarity search for large-scale data. It has competitive search performance when the number of generated hash bits is large, reversely bringing adverse dilemmas for its wide applications. The first purpose of this work is to introduce a novel hash bit reduction schema for hashing techniques to derive shorter binary codes, which has not yet received sufficient concerns. To briefly show how the reduction schema works, the second purpose is to present an effective bit reduction method for LSH under the reduction schema. Specifically, after the hash bits are generated by LSH, they will be put into bit pool as candidates. Then mutual information and data labels are exploited to measure the correlation and structural properties between the hash bits, respectively. Eventually, highly correlated and redundant hash bits can be distinguished and then removed accordingly, without deteriorating the performance greatly. The advantages of our reduction method include that it can not only reduce the number of hash bits effectively but also boost retrieval performance of LSH, making it more appealing and practical in real-world applications. Comprehensive experiments were conducted on three public real-world datasets. The experimental results with representative bit selection methods and the state-of-the-art hashing algorithms demonstrate that the proposed method has encouraging and competitive performance.

A cascaded bit-weighted distribution matching for LDPC-coded PS-64QAM DMT in a high-speed Unamplified IM-DD system

We experimentally demonstrate the generation and transmission of probabilistic shaping (PS) 64-ary quadrature amplitude modulation (64-QAM) discrete multi-tone (DMT) signal with low-density parity-check (LDPC)-coded modulation based on two-stage bit-weighted distribution matching (TS-BWDM) in a high-speed unamplified intensity modulation and direct detection system. The TS-BWDM scheme is based on a two-stage bit-weighted inversion algorithm, which has the advantages of no complex multiplication and division operations and low hardware implementation complexity. As the key content of TS-BWDM, before FEC coding, the bit-weighted intervention operation is used to change the bit probability of a specific sequence in the parallel binary sequence. The two-stage bit-weighted inversion operation and one-stage weight-labeling bit insertion is performed for achieving the target symbol probability distribution. As a result, it does not add a significant amount of extra redundant bits. Additionally, the high-accuracy training symbols-based sampling frequency offset (SFO) estimation method and digital interpolation are used to compensate SFO. In our experiments, the TS-BWDM-based PS-64QAM DMT signals with a net rate of 157.3-Gb/s transmission over 10-km non-zero dispersion- shifted fiber can be achieved. The system performance is investigated under two LDPC code rates (3/4 and 9/10) and three PS parameter values (k = 3, 5 and 9). The experimental results show that the receiver power sensitivity and the system fiber nonlinear effect tolerance can be significantly improved compared with uniformly-distributed signals.

An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC

This paper presents a low-power 18/12-bit 1 MS/s reconfigurable pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC). The proposed pipelined-SAR ADC employs a two-stage SAR structure coupled through a residual amplifier, with the forestage performing 12-bit coarse quantization and the poststage handling 7-bit fine quantization, one bit of redundancy is contained in the rear stage. The input signal is sampled by the first stage, SAR ADC, using the upper plate of a capacitor array and is quantized by charge redistribution. This eliminates the need of additional DACs and subtractors, allowing direct acquisition of the residuals. In addition, the residuals can be amplified by reusing the capacitor array as a switching capacitor. To minimize static power consumption, dynamic logic is adopted in each module of the pipelined-SAR ADC. The calibration of comparator offset and capacitor mismatch is carried out using analog front-end calibration techniques. Implemented in a 180 nm CMOS process, the simulation results show an extra-low power consumption of 1.76 mW with 3.3 V supply voltage and 1 MS/s sampling rate, indicating an exceptional Schreier figure of merit (FOMs) at 181.64 dB. By shutting down the modules of the second-stage SAR ADC, the 18-bit ADC can be dynamically configured as a 12-bit ADC with a sampling rate of up to 5 MS/s.

High capacity double precision image steganography based on chaotic maps

Steganography is the process of hiding confidential information within non-secret multimedia such that the 3rd party cannot distinguish if there is a secret message in it or not. Whereas cryptography is the technique of using mathematical concepts to convert information into unreadable codes via a key. This paper will propose two approaches, lossless and lossy image steganography. Both of them will use cryptography and steganography based on three different chaotic maps to ensure information security. In the cryptography part, two chaotic maps will be used to encrypt the secret information, while in the steganography section, one chaotic map is used to embed the message. The secret information will be concealed in the least significant bits (LSBs) of the double-precision image’s pixels. The double precision image is a high-quality image and can be represented in 64 bits per pixel for grayscale images, leading to a very high redundant bit. Simulation results show a high embedding capacity of 60.938% and 400% for lossless and lossy approaches respectively with a peak signal to noise ratio (PSNR) reach of 69.964 dB. Furthermore, this system is extremely secure due to the use of 3 chaotic maps with key space 2448.

An optimal channel coding scheme for high-speed data communication

This paper presents a novel channel-coding scheme called Binary to Gray Code Conversion based Error Detection and Correction (BGCC-EDAC) code to correct the maximum number of errors that occur at the receiving end during wireless transmission. The proposed method adds the parity bit using Binary to Gray Code Conversion (BGCC). The decoding algorithm proposed in this paper will not perform the regular Gray-to-Binary code conversion. Instead, a novel decoding algorithm is proposed to detect and correct most of the errors in the message bits. It will require retransmission only if any parity error occurs. The efficiency of the proposed channel code stems from its redundant bit calculation and decoding algorithm. The simulation results using Cadence 90 nm technology show that the proposed BGCC-EDAC code consumes low power, less area, and less propagation delay. Simulation analysis using MATLAB reveals that the proposed BGCC-EDAC outperforms the existing error-correcting codes in terms of BER performance. This makes the proposed BGCC-EDAC code, with a shorter code word length, highly suitable for high-speed, reliable data communications.

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma $</tex-math> </inline-formula> and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF). This article presents a calibration-free two-channel TI-NS-SAR with an aggressive second-order NTF for high resolution. Based on a one-time error feedback (FB) at midway, we propose a second-order error-feedforward (FF) to enhance the noise-shaping (NS) effect further meanwhile avoiding the excessive NTF peaking and dynamic range (DR) loss. A dynamic residue amplifier shared between two channels lowers the offset, which reduces the redundant bit to only one bit, thus improving the efficiency of SAR conversion. Fabricated in a 28 nm CMOS with 1 V supply, the prototype achieves 73.2 dB-signal-to-noise-and-distortion-ratio (SNDR) over 30 MHz-BW when operating at 330 MHz. It consumes 3.07 mW and exhibits a Schreier FoM (FoMs) of 173.1 dB.

Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study

This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor’s advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.

A high area-and-energy efficiency 12-bit column-parallel SAR/SS ADC for high-speed infrared focal plane readout circuits with error correction

This paper presents a high-energy-efficiency and high-area-efficiency 12-bit column-parallel successive-approximation-register/single-slope analog-to-digital converter (SAR/SS ADC) for high-speed infrared focal plane readout circuits. The proposed SAR/SS ADC divides the quantization process into upper 8-bit coarse conversion by the SAR ADC and lower 4-bit fine conversion by the SS ADC. The SAR ADC uses the scaled reference-voltage technique to achieve 8-bit conversion using only a 4-bit capacitor DAC. In addition, the SS ADC is designed with an additional 1-bit redundant bit to reduce settling error mismatch between coarse and fine conversion by the proposed error correction method. The proposed SAR/SS ADC is designed in a 0.18μm CMOS process, and each column occupies an area of 30μm×487μm. The post-layout simulation results show that the SAR/SS consumes 73.15 μW for each column and has a DNL of −0.5/+0.6 LSB and an INL of −0.6/+0.4 LSB. The FoM is only 35.72 fJ/step with 2μs conversion time, which achieves an appropriate trade-off between conversion speed, power consumption, and area.

E-SAWM: A Semantic Analysis-Based ODF Watermarking Algorithm for Edge Cloud Scenarios

With the growing demand for data sharing file formats in financial applications driven by open banking, the use of the OFD (open fixed-layout document) format has become widespread. However, ensuring data security, traceability, and accountability poses significant challenges. To address these concerns, we propose E-SAWM, a dynamic watermarking service framework designed for edge cloud scenarios. This framework incorporates dynamic watermark information at the edge, allowing for precise tracking of data leakage throughout the data-sharing process. By utilizing semantic analysis, E-SAWM generates highly realistic pseudostatements that exploit the structural characteristics of documents within OFD files. These pseudostatements are strategically distributed to embed redundant bits into the structural documents, ensuring that the watermark remains resistant to removal or complete destruction. Experimental results demonstrate that our algorithm has a minimal impact on the original file size, with the watermarked text occupying less than 15%, indicating a high capacity for carrying the watermark. Additionally, compared to existing explicit watermarking schemes for OFD files based on annotation structure, our proposed watermarking scheme is suitable for the technical requirements of complex dynamic watermarking in edge cloud scenario deployment. It effectively overcomes vulnerabilities associated with easy deletion and tampering, providing high concealment and robustness.

The Joint Channel Coding and Pre-Distortion Technique on the USRP-Based MIMO-OFDM System

Modern wireless communication systems use orthogonal frequency division multiplexing (OFDM), a multi-carrier modulation method that resists multipath channels and provides bandwidth efficiency. OFDM is generally used with a Multiple-Input Multiple-Output (MIMO) system to boost diversity gain and channel capacity. MIMO-OFDM has several advantages, but its high PAPR value is a drawback. A non-linear high-power amplifier (HPA) can distort signals with high PAPR values. This issue can be resolved by employing predistortion, which compensates for nonlinear HPA. In addition to PD, channel coding can be used to improve the quality of systems with high PAPR values by adding redundant bits to the bits to be sent. In this paper, we report the experimental evaluations of the joint channel coding and pre-distortion (PD) technique on a 2x2 MIMO OFDM system using USRP hardware. The experiments are conducted in two scenarios: line-of-sight (LOS) and nonline-of-sight (NLOS) scenarios. The channel coding used in this scenario is convolutional code with code rates of 1/2, 2/3, and 3/4. From the results of the experiment, it can be seen that the system that uses PD combined with the convolution code produces better performance in the LOS and NLOS scenarios compared to the system without PD. In the LOS scenario, the use of PD can improve the SNR value of code rates 1/2, 2/3, and 3/4 by approximately 58.74%, 75.97%, and 96.20%. In the NLOS scenario, the use of PD can improve the SNR value of code rates 1/2, 2/3, and 3/4 by about 60.71%, 73.59%, and 71.84%. The measurement of the LOS scenario gives a better SNR value than the NLOS scenario, with a maximum SNR value of 30.86 dB, while the maximum SNR value of the NLOS scenario is 30.23 dB. This happened because the LOS scenario suffered minimal multipath fading compared to the NLOS scenario

A Fully Bayesian Approach for Massive MIMO Unsourced Random Access

In this paper, we propose a novel fully Bayesian approach for the massive multiple-input multiple-output (MIMO) massive unsourced random access (URA). The payload of each user device is coded by the sparse regression codes (SPARCs) without redundant parity bits. A Bayesian model is established to capture the probabilistic characteristics of the overall system. Particularly, we adopt the core idea of the model-based learning approach to establish a flexible Bayesian channel model to adapt the complex environments. Different from the traditional divide-and-conquer or pilot-based massive MIMO URA strategies, we propose a three-layer message passing (TLMP) algorithm to jointly decode all the information blocks, as well as acquire the massive MIMO channel, which adopts the core idea of the variational message passing and approximate message passing. We verify that our proposed TLMP significantly enhances the spectral efficiency compared with the state-of-the-arts baselines, and is more robust to the possible codeword collisions.

Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.

CRC-Based Reliable WiFi Backscatter Communiation for Supply Chain Management

Supply chain management aims to achieve both efficiency and low cost. Backscatter technology provides a low-energy consumption approach for critical links in the supply chain, such as warehouse management and cargo identification. Traditional backscatter systems achieve tag data transmission through dedicated hardware or controlled transmission sources. An additional access point (AP) can be used to ensure that the original data are always known in tag data decoding. These requirements increase the deployment costs and are not suitable for large-scale applications. To address these challenges, we introduce CRCScatter, a backscatter system based on a cyclic redundancy check (CRC) reverse algorithm, with an uncontrolled source and a single-AP receiver. The CRCScatter decoder at the receiver uses the constraints within 802.11b WiFi packets to recover the original packet and decode tag data from the backscatter packet. Our Matlab simulation results show that CRCScatter is effective in the low signal-to-noise ratio (SNR) regime, and its average decoding time is independent of the length of tag data. By appending redundant bits in tag data, the decoding accuracy of CRCScatter can be improved. In summary, CRCScatter presents a backscatter communication mode based on ambient WiFi signals with fewer hardware requirements and low deployment costs. Furthermore, the decoding idea of calculating unknown data based on the packet constraints has the potential to expand to different types of excitation packages.

Real-time demonstration of a low-complexity PS scheme for 16QAM-DMT signals in an IM-DD system.

We experimentally demonstrated a low-complexity probabilistic shaping (PS) 16-ary quadrature amplitude modulation (16QAM) scheme based on intra-symbol bit-weighted distribution matching (Intra-SBWDM) for discrete multi-tone (DMT) symbols with field-programmable gate array implementation in an intensity modulation and direct detection (IM-DD) system. Different from the traditional PS scheme such as Gallager many-to-one mapping, hierarchical distribution matching and constant composition distribution matching, the Intra-SBWDM scheme with lower computation and hardware complexity does not need to continuously refine the interval to find the target symbol probability, nor does it need a look-up table, so it does not introduce a large number of extra redundant bits. In our experiment, four PS parameter values (k = 4, 5, 6, and 7) are investigated in a real-time short-reach IM-DD system. 31.87-Gbit/s net bit PS-16QAM-DMT (k = 4) signal transmission is achieved. The results show that the receiver sensitivity in terms of the received optical power of the real-time PS scheme based on Intra-SBWDM (k = 4) over OBTB/20 km standard single-mode fiber can be improved by about 1.8/2.2 dB at the bit error rate (BER) of 3.8 × 10-3, compared to the uniformly-distributed DMT. In addition, the BER is steadily lower than 3.8 × 10-3 during a one-hour measurement for PS-DMT transmission system.

Design of High-Speed SAR ADC based on 40nm CMOS Process

In this paper, a high-speed successive approximation analog-to-digital converter is designed based on a 40 nm CMOS process. A split-capacitor Vcm-Based switching strategy is designed, which is able to keep the output common-mode voltage constant for the DAC capacitor array without using Vcm level drive, while saving half of the capacitance compared to the conventional switching strategy and greatly reducing the area consumption. It also combines the features of binary redundancy technology and non-binary redundancy technology by splitting the highest bit capacitor to the lower bit, which enables the DAC array to generate two additional redundant bits without adding other capacitors, reducing its requirements for noise and establishment accuracy; and it adopts asynchronous timing control without external clocks, which is conducive to improving the speed of SAR ADCs and reducing the design complexity. The designed SAR ADC achieves 9.83 bit effective bits, 60.9 dB signal-to-noise distortion ratio, 77.2 dB spurious-free dynamic range, 1.68 mW overall power consumption, and 18.46 fJ/conv-step superiority at a supply voltage of 1.1 V and a sampling frequency of 100 MHz through simulation.

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

Bio-inspired universal real time image steganalysis

Huge development in communication, innovation and utilization of web has significantly eased exchange of information and the cautioning of prohibited information access is expanding along with it. Due to huge number of the redundant bits, images have become favourable carrier for data hiding technique. The evolution in image steganography had put forward many security ventures such as unofficial data transmission, commercial spy, and terrorist activities. To address this issue, researchers begun to develop mechanisms that can detect the presence of a secret message. Image steganalysis is a counter-measure to image steganography, which starts perceiving what exists inside the transmitted source document. This paper discusses the different methods for Bio-Universal steganalysis proposed by researchers. This paper examines the numerous researchers’ contributions to the field of Universal real time steganalysis.

Efficient Privacy-Preserving Spatial Range Query Over Outsourced Encrypted Data

With the rapid development of Location-Based Services (LBS), a large number of LBS providers outsource spatial data to cloud servers to reduce their high computational and storage burdens, but meanwhile incur some security issues such as location privacy leakage. Thus, extensive privacy-preserving LBS schemes have been proposed. However, the existing solutions using Bloom filter do not take into account the redundant bits that do not map information in Bloom filter, resulting in high computational overheads, and reveal the inclusion relationship in Bloom filter. To solve these issues, we propose an efficient Privacy-preserving Spatial Range Query (PSRQ) scheme by skillfully combining Geohash algorithm with Circular Shift and Coalesce Bloom Filter (CSC-BF) framework and Symmetric-key Hidden Vector Encryption (SHVE), which not only greatly reduces the computational cost of generating token but also speeds up the query efficiency on large-scale datasets. In addition, we design a Confused Bloom Filter (CBF) to confuse the inclusion relationship by confusing the values of 0 and 1 in the Bloom filter. Base on this, we further propose a more secure and practical enhanced scheme PSRQ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> by using CBF and Geohash algorithm, which can support more query ranges and achieve adaptive security. Finally, formal security analysis proves that our schemes are secure against Indistinguishability under Chosen-Plaintext Attacks (IND-CPA) and PSRQ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> achieves adaptive IND-CPA, and extensive experimental tests demonstrate that our schemes using million-level dataset improve the query efficiency by 100x compared with previous state-of-the-art solutions.

The use of SDR as sensor nodes of the intelligent system of management of radio emission data collection

The article is devoted to the study of the use of software-controlled radio (SDR) in the context of the growing demand for wireless technologies and radio-electronic devices. It focuses on the problems of oversaturation of the radio spectrum, the need to automate the management of radio systems, security, the use of machine learning and AI, the integration of various systems, as well as economic benefits. The paper examines the SDR as a tool to address these challenges, particularly due to its ability to operate over a wide frequency range and the use of digital signal processing. The role of SDR in radio monitoring and its importance in identifying and eliminating sources of interference are also revealed. The main attention is paid to the development of the algorithm for performing OFDM-modulation operations in the SDR of intelligent control systems of the radio emission data collection network. The proposed algorithm aims to optimize data transmission, reducing the transmission of redundant bits of information and promoting efficient use of the radio spectrum. The article describes in detail the architecture and functionality of SDR, including an analysis of the impact of OFDM technologies on the efficiency of data transmission within software-controlled systems.

A VHDL Code for Offset Pulse Position Modulation Working with Reed Solomon System by Using ModelSim

Error correction codes, often known as ECC, play a significant part in the process of detecting and correcting data mistakes that occur through communication channels that are unreliable or noisy. The essential concept behind error correction through ECC is to supplement the message that is being sent by the transmitter with redundant bits, the values of which are determined by the parameters n and k. These bits can then be utilized by the receiver to identify and correct specific types of errors. ECC is utilized in a wide variety of applications, including but not limited to data storage, the Internet, and telecommunications. There are numerous variations of ECC, including linear block, convolutional, and turbo codes, among others. The results of a simulation of a linear block reed Solomon, for example, with offset pulse position modulation have been presented in this study. The simulation was carried out in very high-speed integrated circuit hardware description language (VHDL), and a field-programmable gate array was used (FPGA) It made use of a Boolean function to function to program code for an algorithm that is working. Because of its performance, time to market, cost, reliability, and long-term maintenance benefits, FPGA is an appropriate platform for implementing error correction code (ECC). As a part of this project, the technique of offset Pulse Position Modulation (Offset PPM) was invented as an outstanding solution to code the fiber-optic applications and Reed Solomon (RS) codes apply to ModelSim SE-64 10.5 software. In addition, this coding scheme has been approved by the simulation and is matched with theory, and it is expected to be implemented shortly. The study begins with a concise introduction to RS encode/decode about design and performance and then moves on to discuss the development result of simulation and hardware implementation.