Calibration of Cyclic-Pipelined ADCs Using CMOS for Area-Efficiency

Abstract

One of the principal obstacles in the development of pipeline analog-to-digital converters (ADCs) is the imprecision associated with residue amplification. Operational amplifiers (Op-Amps) that possess high gain and speed are recognized for their excessive power consumption, making them unsuitable for employment in proficient analog-to-digital converters (ADCs). The study presents a new method for foreground calibration that addresses amplification differences in cyclic-pipelined ADCs, reducing the need for internal amplifier DC gain. The calibration technique was applied to a cyclic-pipelined ADC with a sampling rate of 2 MS/s and 16-bit resolution. The design of this ADC was optimized for area efficiency, and its fabrication utilized 180 nm CMOS technology. The analog-to-digital converter (ADC) used a 5-bit resolution sub-ADC performing 4 cycles to reduce potential errors. Each cycle contained one bit of redundancy. A fixed-point iterative algorithm was used to find the exact gain for each amplifier. Simulation data shows a SINAD of 100. 6 dB, despite a 57 dB DC gain amplifier. The ADC's active area is 1. 8 mm2 at 30 consumption. 43 mW.