Redundant Bits Research Articles

A Novel Shaping Scheme for PAPR Reduction in Single-Carrier Modulation

A novel PAPR shaping technique intended for systems with high spectral efficiency and single carrier transmission is presented. This technique applies puncturing of error correction redundancy bits to achieve a desired Markovian symbol transmission probability distribution, which avoids symbol sequences with high peak values. For a 16-QAM system with transmission rate of 3 bit/symbol and a root raised cosine (RRC) pulse shape filter with roll-off factor 0.1 and duration of six symbols, an overall gain of about 2.2 dB is demonstrated by simulations using pragmatic binary turbo code for error correction. The technique can be used to improve any single carrier communication link limited by the high power amplifier (HPA) peak power.

Two Dimensional Parity Check with Variable Length Error Detection Code for the Non-Volatile Memory of Smart Data

This paper proposes a novel technology of memory protection for the Non-Volatile Memory (NVM), applied to smart sensors and smart data. Based on the asymmetry of failure rate between the statuses of bit-0 and bit-1 in the non-volatile memory, as a result of the pollution of the radiation of cosmic ray, a two-dimensional parity with variable length error detection code (2D-VLEDC) for memory protection is proposed. 2D-VLEDC has the feature of variable length of redundant bits varied with content of data word in the NVM. The experimental results show that the same error detection quality could be achieved with a 30% redundancy improvement by applying the proposed 2D-VLEDC. The proposed design is particularly suitable for the use of safety-related fields, such as the automotive electronics and industrial non-volatile memories involved in the industrial automation.

Novel Text Steganography Using Natural Language Processing and Part-of-Speech Tagging

The practice of transmitting secret data by using cover data is called steganography. At present, several versatile steganographic methods are available using different digital objects (e.g. image, audio, video, text, etc.) as cover to hide data. Accordingly, many methods of steganalysis have been explored to reveal statistical anomalies in stego object, through which presence of secret data can be detected. However, applications of steganography and steganalysis techniques are challenging when cover object is text, as text does not have any redundant bits. In this paper, an innovative text steganography approach is proposed which uses natural language text as cover as well as secret message. The concept of shared key is also used here, that holds the count of each parts-of-speech of secret message. This key is RSA encrypted and shared with communicative parties. Stego created by this method also is in natural language text. This method is successful as the stego keeps the original meaning of the text in gross which makes it robust and undetectable. It shows good result in capacity ratio; also, the similarity index has been assessed by Jaro–Winkler distance and Generalized Levenshtein distance.

FPGA-based redundancy bits reduction algorithm using the enhanced error detection correction code

To ensure an error-free transmission in packet switching, additional check bits (either header or a payload) are typically appended to the input data of a message for error detection especially in a string of binary code. Normally, it comes from the input message and as a result of a deterministic algorithm after these data have been processed. The receiver system implements the said algorithm, while the transmitter used it to match the reliability of the sent information and detects whether an error bit has occurred or not. The corrupted bits will be corrected, recovered, and matched with the original message. To further improve the detection and correction of the corrupted transmitted bits, an enhanced error detection correction code implementation was proposed and developed in this paper. This will improve the limitations of using cyclic redundancy checking (CRC) code and Hamming code, by reducing the number of the redundancy bits ‘r’ in CRC due to the needed polynomial generator, and the overhead of interspersing of the r in conventional Hamming code, respectively. Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA was used to synthesize the proposed enhanced error detection code (EEDC) method. Based on the results, the transmission rate is faster, and an increase in detection of random errors compared with using CRC and Hamming codes.

Chemical and structural analysis on magnetic tunnel junctions using a decelerated scanning electron beam

Current information technology relies on the advancement of nanofabrication techniques. For instance, the latest computer memories and hard disk drive read heads are designed with a 12 nm node and 20 nm wide architectures, respectively. With matured nanofabrication processes, a yield of such nanoelectronic devices is typically up to about 90%. To date the yield has been compensated with redundant hardware and software error corrections. In the latest memories, approximately 5% redundancy and parity bits for error corrections are used, which increase the total production cost of the devices. This means the yield directly affects the device costs. It is hence critical to increase the yield in nanofabrication. In this paper, we have applied our recently developed method to image buried interfaces in combination with chemical analysis to evaluate magnetic tunnel junctions and have revealed their different magnetoresistance ratios caused by the presence of materials formed at the junction edges. The formation of these materials can be avoided by optimising the junction patterning process to remove residual carbon introduced from resist. Our imaging method with chemical analysis have demonstrated a significant potential for the improvement of junction performance, resulting in higher yields. This can be used as a quality assurance tool in a nanoelectronic device production line.

Lookup Table Algorithm for Error Correction in Color Images

Error correction and error detection techniques are often used in wireless transmission systems. A color image of type BMP is considered as an application of developed lookup table algorithms to detect and correct errors in these images. Decimal Matrix Code (DMC) and Hamming code (HC) techniques were integrated to compose Hybrid Matrix Code (HMC) to maximize the error detection and correction. The results obtained from HMC still have some error not corrected because the redundant bits added by Hamming codes to the data are considered inadequate, and it is suitable when the error rate is low for detection and correction processes. Besides, a Hamming code could not detect large burst error period, in addition, the have same values sometimes which lead to not detect the error and consequently increase the error ratio. The proposed algorithm LUT_CORR is presented to detect and correct errors in color images over noisy channels, the proposed algorithm depends on the parallel Cyclic Redundancy Code (CRC) method that's based on two algorithms: Sarwate and slicing By N algorithms. The LUT-CORR and the aforementioned algorithms were merged to correct errors in color images, the output results correct the corrupted images with a 100 % ratio almost. The above high correction ratio due to some unique values that the LUT-CORR algorithm have. The HMC and the proposed algorithm applied to different BMP images, the obtained results from LUT-CORR are compared to HMC for both Mean Square Error (MSE) and correction ratio. The outcome from the proposed algorithm shows a good performance and has a high correction ratio to retrieve the source BMP image.

Shared intelligent optimum route selection through traffic management system in VANET– SIRS

A Vehicular Ad-hoc Network (VANET) consists of the vehicle to vehicle and vehicle to roadside communication. Growing the density of the vehicles on the road causes flooding while transferring packets from a source to one or multiple destinations over a VANET. However, increasing vehicles on road may causes a problem such as redundancy, congestion, collision and increasing delay though receiving emergency warnings. As long as reliable and proficient multi-hop broadcast in vehicular ad hoc networks is challenging one. In the proposed system commence a new protocol which uses the character of elegant route establishment and selection method for transfer information to the destination (dst) with minimum redundancy, delay and highest bits per second delivery. In some environment vehicles are deployed in a dense manner, and it can move at a high speed. Adjacent Access Points (APs) on the road find out route information from their past report gatherings which use a fuzzy logic to select routing conclusion. This approach consists of isolating the whole network area into clusters. Based on which an optimized route is chosen using the input parameters as vehicle density, distance from the adjacent AP, vehicle mobility, receiving signal strength and delay should be jointly measured in the relay node selection. Though, these computation conflicts with each other depend on vehicle mobility. Hence, we employ fuzzy logic to handle this imprecise information to select forwarding vehicles by mutually taking into account of vehicle distance (d), mobility (v) and Receiving Signal Strength (RSS). The selected vehicle can provide an assure data forwarding with a high competence. The performance of the proposed scheme is evaluated on the metrics such as end-to-end delay, packet delivery ratio by varying vehicle speed, and density of vehicles.

A Novel Architecture of Large Hybrid Cache With Reduced Energy

Energy becomes an inevitable challenge when using a large die-stacking dynamic random access memory (DRAM) cache. Although emerging spin-transfer-torque-RAM (STT-RAM) technology can efficiently reduce the static energy of large cache, it cannot completely replace DRAM cache due to the high write energy of STT-RAM. Recently, researchers have observed that there are many redundant bits written in the row buffer and futile bits written back to STT-RAM cells, which do not change the cells’ value but still cost high write energy. In this paper, we first design a large hybrid cache architecture with the DRAM region and the STT-RAM region to reduce the high static energy of DRAM cache. The selective write back to row buffer and selective write back to cell array optimizations are proposed to reduce high write energy of the STT-RAM region by removing the unnecessary bit-writes. Furthermore, we propose reuse distance-oriented data movement to reduce write operations in the STT-RAM region. Finally, we propose a novel tag design for the hybrid cache by moving all tag arrays to the STT-RAM region. The SPEC CPU2006 benchmarks show an average 28.3% energy reduction and 6.7% performance improvement for the write optimizations and 7.3% energy savings and 27.5% instructions per cycle speedups for the proposed tag design.

Simple Hybrid ARQ Schemes Based on Systematic Polar Codes for IoT Applications

Hybrid ARQ (H-ARQ) schemes enable wireless reliability with high transmission efficiency, which is demanded for battery-operated low-complexity applications, such as Internet of Things. We propose two schemes to enable type-II H-ARQ based on systematic polar codes. We introduce code inversion for polar codes to recover the message from the redundant bits only. The first scheme we propose is an H-ARQ based on half-rate polar codes and code inversion. The second scheme develops a more general H-ARQ technique assuming an arbitrary code rate. We provide a theoretical framework for calculation of the frame error rate in polar codes with incomplete codeword elements. Simulations show that the proposed schemes can achieve a significant performance gain up to 4 dB in terms of throughput efficiency compared with the state-of-the-art H-ARQ scheme used in the high-quality-of-service mode of the IEEE 802.15.6-2012 standard for wireless body area networks.

Redundant Bit Security in RFIDs: Architecture Design and Security Performance Evaluation

This paper presents an analysis of the security performance and evaluation of the hardware architecture of the redundant bit security (RBS) cryptosystem. RBS is a lightweight symmetric encryption algorithm that targets resource-constrained RFID devices. Unlike the existing cryptosystems, RBS simultaneously provides confidentiality, authentication, and integrity of the plaintext by inserting hash-generated redundant bits among the already modified plaintext data. A flexible-length hash algorithm in our optimized hardware architecture allows RBS to support different key sizes which allows flexibility in the security level. Our analysis shows the resilience of RBS against powerful and well-known attacks such as differential attacks and known-plaintext attacks. We compare the performance of the RBS cryptosystem against other distinguished ciphers developed for RFID systems. Simulation results show that RBS results in approximately 100%, 239%, and 153% higher hardware efficiencies while requiring 48%, 56%, and 59% less energy-per-bit compared to H-PRESENT, HB-2, and Grain, respectively. Such results present confirmatory evidence that RBS is a superior solution for providing security in resource-constrained systems such as RFID systems especially when authentication is a priority.

A Novel Interdependent Source-Channel Coding Technique for Enhanced Energy Efficiency in Communication over Wireless Sensor Networks

Reliable energy efficient information transmission is the primary design objective of a Wireless Sensor Network (WSN), considering its unique energy and resource constraints. Energy efficiency and bit error rate (BER) performance are the basic criteria to be taken into account while designing an optimal error correction scheme for WSNs. In this paper, a novel energy efficient error control scheme is proposed which minimizes the energy overheads of a typical error control scheme such as additional bits’ transmit energy and encoding/decoding energy, while achieving a better BER performance compared to the standard schemes. The redundant bits’ transmit energy is saved by incorporating compression and coding energy is minimized by employing simpler operations compared to other schemes. Further,the proposed scheme is validated in the context of mica2 motes. The BER performance and energy consumption of the presented scheme are studied and compared with standard error control schemes,such as, Hamming (7, 4) and RS (31, 29). Simulation results demonstrate the efficacy of the proposed methodology yielding a coding gain (CG) of 4.093 dB with a parameter selection of {30, 7, 2, 5}, in AWGN channel at BER of \(10^{-5}\), as compared to CG of 0.561 dB and 1.485 dB obtained using Hamming (7, 4) and RS (31, 29), respectively. Further, the standard codes above have a redundancy of 75% and 6.9% respectively while the proposed code with the above parameters achieves a compression of 23.81%. Quantification of energy consumption corresponding to each of the above schemes is also provided to prove the energy efficiency of the proposed technique.

Dual image based reversible data hiding scheme using (7,4) hamming code

In this paper, we propose a new dual-image based reversible data hiding scheme through (7,4) Hamming code (RDHHC) using shared secret key. A block of seven pixels are collected from cover image and copied into two arrays then it is adjusted redundant Least Significant Bits (LSBs) using odd parity such that any error creation is encountered at the sender end and recovered at the receiver end. Before data embedding, we first complement the bit at shared secret position. After that, secret message bit is embedded by error creation caused by tamper in any suitable position except secret position and that error is detected as well as corrected at the receiver end using Hamming error correcting code. One shared secret position κ and one shared secret key ξ help to perform data embedding, data extraction and recovery of the original image. The secret data and original cover image are successfully recovered at the receiver end from dual stego image. Finally, we compare our scheme with other state-of-the-art methods and obtain reasonably better performance in terms of PSNR.

A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS

This brief presents a 0.3-V energy-efficient 10-bit successive approximation register analog-to-digital converter. A shifted monotonic switching procedure is proposed to achieve an average digital-to-analog converter switching energy of 63.75 CV2. Two redundant bits are implemented with error tolerance of ±12 mV for dynamic comparator offset and common-mode reference (Vcm) sensitivity. The prototype is designed and fabricated in a 90-nm CMOS with a core size of $250 \mu\text{m}\times 50 \mu\text{m}$ (0.0125 mm2). At 250 KS/s and Nyquist rate input, it consumes 52.3 nW at 0.3-V supply with an achieved signal-to-noise-and-distortion ratio of 51.21 dB and a resulting figure of merit of 0.705 fJ/conv.-step.

Secure Wireless Image Communication Using LSB Steganography and Chaotic Baker Ciphering

The popularity of wireless multimedia applications in real life and the open nature of wireless media for access make the security of confidential multimedia over wireless channels a major task. This paper proposes a two multi-layer security algorithm using steganography with encryption that strengthens the image security through its transmission over a wireless channel. The steganography conceals the data existence within a cover medium, while the encryption hides the data meaning by using specific algorithms. The suitability of image as a cover medium is due to abundance of redundant bits, and bulk data capacity. The chaos based encryption algorithms are adopted in this paper. In this work a confidential image is embedded into a cover image using least significant bit steganography, and then the output stego image is encrypted using a 2-D Logistic map or 2-D chaotic Baker map. The encrypted stego image is then transmitted over a wireless AWGN channel and the reverse processes are implemented to extract the received secret image. Several experiments have been carried out to examine the suitability of the proposed algorithms for securing high sensitivity images through transmission over wireless channels at different noise levels.

A New Squarer design with reduced area and delay

Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less amount of hardware, propagation delay and power consumption. Our work proposes an efficient algorithm using literals minimisation technique to achieve squaring with improved performance with respect to area, delay and power. This technique compares favourably with the recent work by offering less gate delay, transistor count and area. The proposed optimisation algorithm has been verified using different Xilinx and Altera Field Programmable Gate Array device family. Simulation results show better performance of our technique than the work shown in the past work in respect of delay, power and area. Moreover the proposed technique has been compared with the well known Radix-4 Booth encoded squarer technique. Further, application specific integrated circuit (ASIC) implementation has been performed and the performance parameters have been compared with the earlier work and that also establishes the better results for our technique.

Proxy Bits for Low Cost Floating-Point Fused Multiply–Add Unit

A new floating-point fused multiply–add (FMA) unit is proposed in this paper. We observed a group of redundant bits that have no effect on the effective results of the floating-point FMA arithmetic, and figured out that two proxy bits can replace the redundant bits. We proved the existence of the proxy bits using binary arithmetic keeping track of the negligible bits. Using proxy bits, the proposed FMA unit achieves improvement in terms of cost, power consumption, and performance. The results show that the proposed FMA unit reduces the total area and latency by approximately 17.0% and 32% respectively, compared with a current widely used FMA unit.

Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods

Two new parallel bus coding methods for generating a DC-balanced code with additional bits are proposed to achieve the self-stabilization of the intermediate power level in Stacked-Vdd integrated circuits. They contribute to producing a uniform switching current in parallel inputs and outputs (I/Os). Type I coding minimizes the difference in the number of switchings between the upper and lower CMOS I/Os by 8B/10B coding followed by toggle conversion. Type II coding, in which the multi-value running disparity control feature is integrated into the bus-invert coding, requires only one redundant bit for any wider bus. Their DC-balanced feature and the stability effect of the intermediate power level in the Stacked-Vdd structure were experimentally confirmed from the measurement results obtained from the developed test chips.

Performance Analysis of Reed-Solomon Codes Concatenated with Convolutional Codes over AWGN Channel

With rapid growth in today’s technology, digital communication is playing a major role to provide hostile environment to meet various applications. In this communication, Coding plays a prominent role to contribute error free transmission through channel coding which improves capacity of a channel by adding some redundant bit to the original information. One way to provide a better performance of the communication system is by concatenating different types of channel coding techniques. The concatenation can be done either in parallel or serial. The primary aim of this paper is to concatenate the Reed-Solomon codes with Convolutional codes in series, which provides better results comparing with single coding techniques. The performance of the concatenation of Reed-Solomon codes with Convolutional codes can be evaluated by finding bit error rate with various values of signal-to-noise ratio over AWGN channel. The analytical result has been obtained by using MATLAB/OCTAVE.

Performance Analysis of Reed-Solomon Codes Concatenated with Convolutional Codes over AWGN Channel


 
 
 With rapid growth in today’s technology, digital communication is playing a major role to provide hostile environment to meet various applications. In this communication, Coding plays a prominent role to contribute error free transmission through channel coding which improves capacity of a channel by adding some redundant bit to the original information. One way to provide a better performance of the communication system is by concatenating different types of channel coding techniques. The concatenation can be done either in parallel or serial. The primary aim of this paper is to concatenate the Reed-Solomon codes with Convolutional codes in series, which provides better results comparing with single coding techniques. The performance of the concatenation of Reed-Solomon codes with Convolutional codes can be evaluated by finding bit error rate with various values of signal-to-noise ratio over AWGN channel. The analytical result has been obtained by using MATLAB/OCTAVE.
 
 

Performance Analysis of PAPR Reduction in 4×4 Spatially Multiplexed MIMO-OFDM System using SLM and Optimum-PTS Techniques

Multiple-input Multiple-output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) is a promising candidate for 4G high-data-rate broadband wireless communications. However, MIMO-OFDM inherited the problem of high Peak-to-Average Power Ratio (PAPR) from OFDM which leads to in-band distortion, undesired spectral spreading, low power efficiency and increases the cost of the RF power amplifier. Many PAPR reduction techniques were developed in last two decades to reduce the PAPR of OFDM, among them Partial Transmit Sequence (PTS) and Selected Mapping (SLM) are the important ones. This paper proposes two PAPR reduction technique; SLM and Optimum -PTS for reducing the PAPR and does performance comparison of these two techniques on the basis of reduction in PAPR level, BER and the number of redundant bits required. It shows that the use of Optimum-PTS technique with QPSK modulation comprising of 128 subcarriers provides better PAPR reduction and good BER as compared to SLM.