A New Squarer design with reduced area and delay

Abstract

Digital multiplier and squarer circuits are indispensable in digital signal processing and cryptography. Using multiplier, the partial products of the squarer are generated which are added to achieve the final output. But the implementation of squaring has the advantage that we can avoid the generation of many partial products by eliminating the redundant bits, thus resulting the circuit to be simpler with less amount of hardware, propagation delay and power consumption. Our work proposes an efficient algorithm using literals minimisation technique to achieve squaring with improved performance with respect to area, delay and power. This technique compares favourably with the recent work by offering less gate delay, transistor count and area. The proposed optimisation algorithm has been verified using different Xilinx and Altera Field Programmable Gate Array device family. Simulation results show better performance of our technique than the work shown in the past work in respect of delay, power and area. Moreover the proposed technique has been compared with the well known Radix-4 Booth encoded squarer technique. Further, application specific integrated circuit (ASIC) implementation has been performed and the performance parameters have been compared with the earlier work and that also establishes the better results for our technique.