Reduction Of Short Channel Effects Research Articles

Split gated silicon nanotube FET for bio‐sensing applications

A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current (ION) and the threshold voltage (Vth) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive simulations have been done using the SILVACO ATLAS. Sensitivity analysis has been carried out by considering half-filled and full-filled nanogaps with the neutral or charged biomolecules inside the cavity. Significant sensitivity and excellent reduction in short-channel effects has been observed in proposed biosensor.

Electrostatic and radio frequency performance investigation of δ-doped In0.53Ga0.47As/InP stepped poly gate metal oxide semiconductor field effect transistor

A δ-doped stepped poly gate heterostructure metal oxide semiconductor field effect transistor (HMOSFET) has been analysed. The insertion of a δ-doped layer within the channel region of the proposed In0.53Ga0.47As/InP HMOSFET results in the reduction of short channel effects and the junction capacitance. In the proposed device, the split gate with dissimilar oxide thickness from the source end to drain end have p+ poly in first and third region whereas, n+ poly is in the second region. Further, the δ-doped layer within the channel in stepped poly gate HMOSFET significantly enhances the electrical characteristics of the device. Simulation results reveal that in comparison with stepped poly gate and conventional HMOSFET, δ-doped stepped poly gate HMOSFET gives improved electron transport phenomena and analog characteristics in terms of electron mobility, electric field, electron velocity, transconductance, On resistance, transconductance generation factor and switching ratio. Further, reduction in junction capacitance improves the radio frequency performance metrics in terms of cut-off frequency, maximum frequency and gain bandwidth product.

Assessment of interface traps in In 0.53 Ga 0.47 As FinFET with gate‐to‐source/drain underlap for sub‐14 nm technology node to impede short channel effect

Silicon fin field-effect transistor (FinFET) devices with gate–source/drain underlap fin length (Lun) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In0.53Ga0.47As material. Three-dimensional technology computer-aided design simulations for 14 nm channel length In0.53Ga0.47As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for Lun = 0, 3, 6, and 9 nm with interface trap density of 1012 and 1014 cm–2 eV–1. Improvement in the subthreshold swing (SS) is observed as the Lun increases but at the cost of intrinsic delay. However, the improvement in SS after Lun = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the Lun increases till 6 nm after that this improvement is not very significant.

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

New dual material double gate junctionless tunnel FET: Subthreshold modeling and simulation

A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant parameters such as surface potential, electric field, threshold voltage, drain current, transconductance-to-drain current ratio, subthreshold slope and subthreshold swing are extracted from the 2-D analytical solution of Poisson's equation. Relating DMDG JLTFET to Junctionless MOSFETs, the results show significant reduction of Short Channel Effects (SCEs) at the drain end. The analytical model for DMDG JLTFET is effective due to the combined supremacy of uniform doping in the channel, usage of high-K gate dielectric material and work function engineering in the gate metal. The results obtained from the analytical model are simulated and validated using 2-D Sentaurus TCAD device simulator.

Improved Switching Speed of a CMOS Inverter Using Work-Function Modulation Engineering

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family.

비대칭 DGMOSFET에서 터널링 전류가 채널길이에 따른 문턱전압이동에 미치는 영향

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor

In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results show that the PGFET offers significant reduction in short channel effects and variability due to utilization of uniform lightly doped silicon nanowire (SiNW) as compare to highly doped silicon nanowire in junctionless transistors. The performance parameters were evaluated for different device geometries, such as variation in SiNW radius, equivalent oxide thickness, channel length and spacer length. Sensitivity analysis shows that the PGFET exhibits less dependence towards gate length in comparison to other device parameters. It is seen that ON to OFF current ratio variation with silicon nanowire thickness is lower for PGFET as compared to JLFET. The threshold voltage roll-off and sensitivity towards intrinsic delay in PGFET is much lower than its counterpart device.

Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE

In this paper, we propose a new two-dimensional (2-D) analytical model of dual material junctionless surrounding gate MOSFET (DMJLSRG MOSFET). The expressions of potential and Electric Field of the gate engineered MOSFET structure have been obtained by solving the 2-D Poisson’s equation in subthreshold regime using a parabolic potential approximation considering effective conduction path effect (ECPE). The developed potential model accurately predicts the perceivable step function in the potential profile, responsible for effective screening of the drain potential variation in order to reduce DIBL and threshold voltage roll-off. In this work, effectiveness of dual material gate engineered (DM) design for junctionless MOSFET was scrutinized by comparing the results with a single material gate junctionless surrounding gate MOSFET (SMJLSRG MOSFET) of same dimension. From the developed potential model, a simple and accurate analytical expression of threshold voltage is also derived. Results reveal that DMJLSRG devices offer superior performance as compared to SMJLSRG devices. An improvement of hot-carrier effects (HCEs) and a reduction of short-channel effects (SCEs) have been demonstrated for gate-engineered DMJLDG device over the corresponding conventional (SMJLDG) device. The proposed model can be used as a basic design guideline for gate-engineered junctionless surrounding gate MOSFETs.

InGaAs (110) Surface Cleaning Using Atomic Hydrogen

A major obstacle facing III-V semiconductor based metal oxide semiconductor field effect transistors (MOSFETs) is the large density of trap states that exist at the semiconductor/oxide interface.[1] These trap states can pin the Fermi level preventing the MOSFET from acting as a switch in logic devices. Several sources of Fermi level pinning have been proposed including oxidation of the III-V substrate.[2, 3] In order to minimize the presence of III-V oxides it is crucial to employ either an ex-situ etch or to use an in-situ method such as atomic hydrogen cleaning.[4, 5] Although atomic H cleaning of III-V surfaces is well known, it has never been demonstrated on InGaAs (110) crystallographic faces. Furthermore, tri-gate field effect transistors (finFETs) have recently been employed in commercially available logic chips.[6] This unique device architecture allows for a reduction in short channel effects, minimization of the subthreshold swing, and a higher transconductance.[7] The InGaAs (110) surface would be the sidewalls of a vertically aligned (001) based finFETs.[8] Therefore, it is essential to find an in-situ method to efficiently remove any oxides or contamination from the (110) surfaces that is also compatible with the (001) surface. In this study, STM was employed to determine if atomic hydrogen can be used to remove the native oxide from air exposed InGaAs (110) samples. A post clean anneal was used to restore the surface to molecular beam epitaxy (MBE) levels of cleanliness.

Analytical Modeling and Simulation of Dual Material Gate Tunnel Field Effect Transistors

In this paper, a new two dimensional (2D) analytical model of a Dual Material Gate tunnel field effect transistor (DMG TFET) is presented. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expressions for surface potential and electric field are derived. The electric field distribution can be used to calculate the tunneling generation rate and numerically extract tunneling current. The results show a significant improvement of on-current and reduction in short channel effects. Effectiveness of the proposed method has been confirmed by comparing the analytical results with the TCAD simulation results.

Analytical approach of a nanoscale triple-material surrounding gate (TMSG) MOSFETs for reduced short-channel effects

A 2D analytical model for the triple material surrounding gate MOSFET (TMSG) is developed by solving the Poisson equation. In this structure, we use three gate materials of different work functions. The model includes analytical modeling of parameters like surface potential, Electric field distribution and threshold voltage using parabolic approximation method. The short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. The small difference of voltage due to different gate material keeps uniform electric field along the channel, which in turn improves the carrier transport efficiency. Hence the reduction of short channel effects (SCEs) are studied by modeling the device. The results of the analytical model are compared with the MEDICI simulation results and it is well validated.

Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation

In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.

Modeling of Drain Current for Grooved-Gate MOSFET

A drain current model of grooved-gate MOSFET which is based on the difference of the channel depth distance along the channel from the source to the drain in cylindrical coordinate is presented in this paper. From the analysis, the potential of grooved-gate is related to geometry structure parameters the angle (Ѳ0) and radius (r0) of concave corner as well as channel depth (d). The presence of corner effect will influence to the drain potential, drain current characteristics as well as the other electrical characteristics, such as conductance (gm) and transconductance (gd). In this result, model shows effect of corner with improvement of the device the characteristics especially the reduction of short channel effect (SCE) althought drain current value grooved-gate MOSFET of is slightly less than the ordinary MOSFET.

Reduction of Short Channel Effects and Hot Carrier Induced Instability in Fully Self-Aligned Gate Overlapped Lightly Doped Drain Polysilicon TFTs

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

InAlN/GaN HEMTs With AlGaN Back Barriers

This letter studies the effect of AlGaN back barriers in the dc and RF performance of In0.17Al0.83N/GaN high-electron mobility transistors grown on SiC substrates. When compared to conventional structures without a back barrier, the back barrier effectively prevents the degradation of drain-induced barrier lowering and significantly improves the output resistance in sub-100-nm-gate-length devices. The reduction in short-channel effects helps to increase the frequency performance of AlGaN back-barrier devices. For a 65-nm gate length, the current gain cutoff frequency (fT) of a transistor with an AlGaN back barrier is 210 GHz, which is higher than that of the standard device with the same gate length (fT = 195 GHz).

Simulation of High–&lt;I&gt;κ&lt;/I&gt; Dielectrics in Counter Doped Double Gate Metal Oxide Semiconductor Field Effect Transistors

With the continued scaling of the SiO 2 thickness below 2 nm in Double Gate MOSFET devices, a large direct-tunneling current flows between the gate electrode and silicon substrate is highly affecting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. The counter doped (p-type) Double Gate MOSFETs with high-κ gate dielectric material is modeled to obtain the transport characteristics, DIBL, I on /I off ratio, threshold voltage and subthreshold leakage current. Reduction of short channel effects are observed in counter doped (p-type) DG MOSFET with high-κ dielectrics. Drain induced barrier lowering (DIBL) is reduced to ≈25%, subthrehold leakage current is decreased to ≈50%, I on /I off ratio is increased to ≈75% and threshold voltage (V t ) is increased to ≈6% in 1 nm dielectric thickness T ox . Results show that counter doped DG MOSFETs with high-κ gate dielectric material is an effective method to reduce the short channel effects.

테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of , 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

Full-Band Particle-Based Analysis of Device Scaling for 3D Tri-Gate FETs

In this paper, a 3D tri-gate SOI FET with a wrap around gate geometry is studied using a full-band particle-based simulation tool as stated in M. Saraniti et al. (1999) Tri-gate FETs show superior scalability over planar device structures, including a reduction of short channel effects based on F. Yang et al. (2002). The 3D gate structure of the tri-gate FET not only plays a role in reducing DIBL by shielding the electric field lines from the drain, but also improves gate-channel controllability.

Source engineering in short channel double gate vertical SiGe-MOSFETs

Transistor channel lengths are being continually scaled to smaller dimensions to improve the high-frequency performance and package density, which will lead to the introduction of sub-50 nm gate lengths in production in the near future. In this paper, the performance of a double gate (DG) vertical metal oxide semiconductor field effect transistor (MOSFET) using strained-SiGe as the channel has been analyzed using simulation. The advantages of the band gap engineering and the vertical structure are shown in terms of (a) independence of channel length, (b) independence of source-drain bias, (c) improved device characteristics (lower off-current), (d) reduction of short channel effects, and (e) suitability for low-power operation.