Reduce Power Dissipation Research Articles

(Invited) Physical Understanding and Prevention of Bipolar Degradation in SiC Power Devices

Through recent progress in SiC technology, 1–3 kV-class SiC power devices (field effect transistors and Schottky barrier diodes) have been commercialized, demonstrating remarkable reduction of power dissipation in various electric systems. However, “bipolar degradation” caused by forward conduction of pn junctions has not been completely solved [1]. In this paper, physical understanding and prevention of the bipolar degradation in SiC devices are reviewed.Degradation in SiC bipolar devices is caused by expansion of a single Shockley-type stacking fault (SSF) in {0001} from a basal plane dislocation (dislocations lying on a {0001} plane) through minority carrier injection and subsequent recombination [2]. The authors conducted careful observation and theoretical analyses on the shapes of expanded SSFs in SiC upon minority carrier injection, and clarified 36 different types of SSFs [3]. For fabrication of high-reliability SiC devices, any basal plane dislocations must be eliminated from a lightly-doped voltage-blocking layer, where a high density of excess carriers is injected during device operation. The authors carried out a number of SiC epitaxial growth runs by using a custom-made chemical vapor deposition system and discovered that almost all the basal plane dislocations can be converted to threading edge dislocations in the initial stage of SiC epitaxial growth (dislocation conversion occurs near the epilayer/substrate interface). The typical density of basal plane dislocations in SiC epitaxial layers was 1–10 cm-2, but the density could be reduced to 0.1 cm-2 or less by increasing the growth rate from 5 to 24 µm/h on 4 degrees off-axis SiC(0001) substrates without any conflicts in the surface morphology and doping control (see the attached image). The achieved dislocation density (< 0.1 cm-2) is low enough to fabricate 1 cm2 devices (300–400 A devices) free from the degradation phenomenon. A basal plane dislocation and a threading edge dislocation can possess the same Burgers vector, which is the reason why the dislocation conversion can take place. It is also noted that a threading edge dislocation, which runs along <0001> (perpendicular to the {0001} plane), does not affect the performance and reliability of SiC devices, at least, within operation conditions in practical applications.It has been experimentally revealed that a SSF can either expand or contract, depending on the current density and temperature. Thus, it is essential to clarify the critical condition where SSF expansion starts. The authors developed a physics-based model to calculate the effective formation energy of a SSF in SiC, taking account of the electronic energy gain by forming a SSF under minority carrier injection [4]. Here a SSF exhibits a slightly smaller bandgap than the perfect SiC and a SSF behaves like a quasi-quantum well in SiC. It can be judged that SSF expansion takes place when the effective SSF formation energy is negative, by which the free energy is lowered by SSF expansion [5].The effective SSF formation energy was calculated as a function of the injected excess carrier density at different temperatures. When the carrier density is low, the SSF formation energy is close to the value in equilibrium (4.7 mJ/m2 [6]). As the carrier density increases, the SSF formation energy turns to be negative due to the electronic energy gain, and the critical excess carrier density above which SSF expansion occurs can be determined as about 5E14 cm-3 at 300 K from this calculation. This critical carrier density gradually increases with elevating the temperature, due to the enhanced emission of electrons from an SSF and thereby a lowered energy gain. The critical carrier density was experimentally determined through observation of SSFs in fabricated SiC pn diodes operating at different current densities and temperatures. The critical carrier density experimentally determined was 4E14 cm-3 at room temperature, being a very good agreement with the theoretical prediction mentioned above. Therefore, the developed model serves as a guideline for preventing bipolar degradation. Based on these results, nearly perfect prevention of bipolar degradation can be achieved by introducing a “recombination-enhancement layer” between a voltage-blocking layer and a substrate, the detail of which shall be explained at the conference.[1] T. Kimoto and H. Watanabe, Appl. Phys. Express, 13, 120101 (2020).[2] M. Skowronski and S. Ha, J. Appl. Phys., 99, 011101 (2006).[3] A. Iijima et al., Philos. Mag., 97, 2736 (2017).[4] A. Iijima and T. Kimoto, J. Appl. Phys., 126, 105703 (2019).[5] K. Maeda et al., Mater. Sci. Forum, 725, 35 (2012).[6] K. Maeda et al., Appl. Phys. Express, 14, 044001 (2021). Figure 1

Chip-level design for intelligent human position detection based on PIR sensor

PurposeThis study aims to present a novel technique to localize the human position in a room, to manage people in a specified space.Design/methodology/approachIn this study, a real-time human sensing detection and smart lighting control was designed within a single silicon core. The chip has been successfully realized within 1.5 mm2 silicon area using TSMC 0.25 um process.FindingsThis chip can read the weak signal of pyroelectric infrared (PIR) sensor to find the position of human body in a dark room and then help control the smart lighting system for an intelligent surveillance system.Originality/valueThis chip presented the retriggering delay control to expand the LED lighting time infinitely to avoid lighting-off suddenly while users stay on a space. This function is very useful in a practical intelligent surveillance system that is mainly based on human detection to better reduce power dissipation and memory space.

A 100-MHz 3.352-mW 8-bit shift register using low-power DETFF using 90-nm CMOS process

ABSTRACT By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock’s opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip’s functionality and jitter measurement at the maximum frequency of 200 MHz.

A low reference voltage interference 10-bit cyclic ADC based on current sub-DAC

A 10-bit cyclic ADC with current sub-DAC for column readout of CMOS image sensors (CIS) is presented in this paper. By charging and discharging sampling capacitors with current, reference voltages are static and stable, and thus the proposed cyclic ADC is suitable to be adopted in large-array readout circuit of CIS. The proposed cyclic ADC is designed in 0.11 μm 1-poly 4-metal CMOS technology. Large-array readout circuit of CIS based on the proposed cyclic ADC was simulated. According to the results of simulation, the proposed cyclic ADC under 3.3/1.5 V supply voltages achieves +0.30/-0.50 LSB maximum differential non-linearity (DNL), +0.80/-1.30 LSB maximum integral non-linearity (INL). It shows a 60.6 dB signal-to-noise and distortion ratio (SNDR) at 333 kS/s sample rate. Meanwhile, the proposed cyclic ADC can work stably at different process corners. The root mean square error (RMSE) of the transient positive reference voltage is 28 mV and it's 27 mV of the transient negative reference voltage. The proposed design effectively reduces the reference voltage fluctuation. Compared with the traditional 333 kS/s 10-bit cyclic ADC, the proposed one can reach the same analog to digital conversion accuracy and reduce power dissipation by 16%.

A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology

Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.

Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node

ABSTRACT Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices over the past few decades, power consumption has increased tremendously. To reduce power dissipation at lower technology nodes, digital logic circuits are designed with modern (FinFET) devices. In this paper, FinFET INDEP (input dependent) technique-based short gate (SG) FinFET Adder circuits are proposed at 10 nm technology node. The performance comparison of INDEP technique-based adder circuits is done with the SG FinFET adder circuits. The analysis of adder circuits is performed first in terms of functional verification (transient characteristics) and finally for different performance parameters such as propagation delay, power dissipation and power delay product (PDP). The proposed FinFET INDEP technique proves as one of the best leakage reduction techniques for FinFET adder circuits at lower technology nodes. To test the reliability of the circuits, Monte Carlo analysis is also performed. The PDP is improved by 16.8% and 13.73% in INDEP SG FinFET half adder(HA) and INDEP SG FinFET full adder(FA) at 10 nm technology, respectively, in comparison with the ones without INDEP technique. The Monte Carlo simulation results with 3σ Gaussian distribution at ±10% process, voltage and temperature variations show the improvement in PDP in case of SG INDEP FinFET FA and SG INDEP FinFET HA circuit in comparison to SG FinFET FA and FinFET HA circuit, respectively. Simulation is performed using HSPICE tool at 10 nm process technology node.

Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.

A Spherical Harmonics Decomposition Method (SHDM) for Irregular Matrix Coils Design.

With advantages of reduced coupling and compact structure, Matrix Coils (MCs) design extension to approximate multiple target inhomogeneities is necessary to improve its performance in shimming applications. A Spherical Harmonics Decomposition Method (SHDM) is proposed for the multi-target MCs optimization problem. The magnetic field generated by the MCs is represented in form of SHs' orthogonal basis, based on which the MCs pattern is optimized to adapt to multiple SH targets. With multi-target SHs of the 1st, 3rd, and mixed 1st&2nd degrees in Halbach magnet shimming, MCs structure optimizations were successfully performed. Comparisons with regular interleaved MCs show the optimized coil structure provides better performance, including reduction of power dissipation, maximum current amplitude, and total current requirement. This work proposed a simple and intuitive way of irregular MCs optimization, which is of high benefits in compact MR systems based on permanent magnets. This methodology may also be translated into local gradient & shimming matrix coils designs for conventional magnetic resonance device.

Impedance and Dielectric Properties of PVC:NH4I Solid Polymer Electrolytes (SPEs): Steps toward the Fabrication of SPEs with High Resistivity.

In the present article, a simple technique is provided for the fabrication of a polymer electrolyte system composed of polyvinyl chloride (PVC) and doped with varying content of ammonium iodide (NH4I) salt using solution-casting methodology. The influences of NH4I on the structural, electrochemical, and electrical properties of PVC have been investigated using X-ray diffraction, electrochemical impedance spectroscopy (EIS), and dielectric properties. The X-ray study reveals the amorphous nature of the polymer–salt complex. The EIS measurement revealed an ionic conductivity of 5.57 × 10−10 S/cm for the electrolyte containing 10 wt.% of salt. Our hypothesis is provided, which demonstrated the likelihood of designing highly resistive solid electrolytes using the concept of a polymer electrolyte. Here, the results showed that the resistivity of the studied samples is not dramatically decreased with increasing NH4I. Bode plots distinguish the decrease in resistance or impedance with increasing salt contents. Dielectric measurements revealed a decrease in the dielectric constant with the increase of NH4I content in the PVC polymer. The relaxation time and dielectric properties of the electrolytes confirmed their non-Debye type behavior. This pattern has been validated by the existence of an incomplete semicircle in the Argand plot. Insulation materials with low εr have found widespread applications in electronic devices due to the reduction in delay, power dissipation, and crosstalk. In addition, an investigation of real and imaginary parts of electric modulus leads to the minimized electrode polarization being reached.

Undoped Drain Graded Doping (UDGD) based TFET design: An innovative concept

The work deals with the implementation of charge plasma concept towards the formation of graded doping profile in the Drain region of Tunnel FET (TFET) device architecture. This new and innovative concept of graded doping profile in the lateral direction holds its merit towards stopping the ambipolar conduction in TFETs without affecting its off and the on state performance. The proposed device i.e. Undoped Drain Graded Doping based TFET (UDGD TFET) architecture is highly effective in suppressing the gate to drain and therefore the total gate capacitance values and thus also seems promising towards reduction in the dynamic power dissipation in TFETs. The architecture has also shown significant improvements for RF application in terms of cut-off frequency, Gain Bandwidth and Transit Time with optimized parameters such as gate work function, drain workfunction, channel length and drain region length when compared to conventional Tunnel FETs.

Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation

This paper focuses on the design of the conventional CMOS digital circuits and the Multi-Threshold CMOS (MTCMOS) digital circuits, which perform the specific Boolean logic function, as well as the comparison between these designing techniques by their functionality and power consummation (dissipation). The leakage of currents in integrated circuits based on CMOS logic becomes quite significant when the complementary MOS transistors are the small-device geometries (small dimensions), and this effect imposes alternative techniques that enable the designing of CMOS digital circuits with low-power dissipation, even in standby mode. One of these techniques is the design of the CMOS digital circuits with multi-threshold voltage (MTCMOS), which enables the reduction of the leakage power dissipation, as a part of the overall power dissipation in CMOS logic. Two CMOS digital circuits are designed (2-input XNOR CMOS gate and the other one is the CMOS gate that performs a complex Boolean function) based on conventional CMOS technique and multi-threshold voltage CMOS technique, and their functionality and calculation of the average overall power dissipation are tested using the Computer-Aided Design (CAD). The methodology used to achieve low power dissipation in CMOS digital circuits (MTCMOS) will be an efficient method for reducing the overall dissipation, while the high speed performance will be maintained.

Comparative analysis of STT and SOT based MRAMs for last level caches

In recent years, magnetic RAMs have stimulated considerable research interest due to its high area-density and low leakage-power with comparable speed that makes it a strong contender for possible replacement of conventional RAMs. However, the operational speed of MRAM is relatively lower than the SRAMs. Advanced switching mechanism such as Spin Transfer Torque (STT), Voltage-Controlled Magnetic Anisotropy (VCMA), Magneto Electric (ME) effect, and Spin-Orbit Torque (SOT) has been introduced to further improve the speed of operation. This paper explores the comparative analysis of STT and SOT-based MRAMs for the application of Large Last-Level Caches (L3Cs). It will give an insight into the MRAM from device to architectural level, in-aspect of performance parameters such as read-write energy consumption, leakage power, chip-area and read-write latency. This research work is carried out through a benchmarked simulation framework, starting from device to architectural level. At the cell level, it is observed that STT-MRAM takes 50% less area with 74% reduction in leakage power dissipation as compared to SOT-MRAM. However, the SOT-MRAMs is 4× faster than the STT-MRAM. At the architectural level, SOT-MRAM outperforms STT-MRAM in terms of read/ write energy and latency at the cost of marginal chip-area and leakage-power. Overall, in comparison to its conventional counterpart (SRAMs), SOT MRAMs are proved to be a superior candidate at a large size of LLCs in all aspects.

A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error

In this paper, a novel implementation is proposed for the Delayed LMS (DLMS) filter, able to reduce the power dissipation while preserving regime performances. The approach relies on the observation that the error signal is small in magnitude and oscillates around zero when the circuit is close to the convergence point. Therefore, the most significant bits of the error signal continuously toggle from positive to negative values causing high switching activity in the multipliers of the feedback section. This paper proposes to employ a sign-modulus representation of the error signal, to substantially reduce the switching activity of the feedback path of the filter. Additional approximation techniques are also devised to further reduce power dissipation. Comparisons with the state-of-the-art show that the proposed filter is the only one able to approach the MSE of the exact implementation with a remarkable reduction of power dissipation. A test-chip in TSMC 28nm CMOS technology has been realized to experimentally verify the validity of our technique. The experimental results show the possibility of saving up to 45.4% of power consumption with respect to the exact implementation of the filter.

A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier

Decimal computation is highly demanded in many human-centric applications such as banking, accounting, tax calculation, and currency conversion. Hence the design and implementation of radix-10 arithmetic units attract the attention of many researchers. Among the basic decimal arithmetic operations, multiplication is not only a frequent operation but also has high complexity and considerable power consumption. Therefore, this paper concentrates on this issue and studies a general design methodology that reduces power/energy consumption via localizing switching activity without compromising target performance. This method decomposes a digit multiplier into smaller ones, like Karatsuba’s algorithm, while the multiplicand and the multiplier can be partitioned into different sizes. We take advantage of various size partitions in two types of symmetric and asymmetric, which final designs provide specific characteristics. All designs were implemented using VHDL and synthesized in the Design-Compiler toolbox with TSMC 130 nm Technology file. The results are significant; in respect to the original design, by a random test vector, 25% power reduction is achieved with no effect on latency and a negligible area penalty. Moreover, the experimental results indicate a potential for considerable reduction of power dissipation based on statistical properties of possible input data.

PCB Transducer Coil Design for a Low-Noise Magnetic Measurement System in Space Missions

Here a minimum power dissipation coil transducer has been designed to allow in-flight noise characterization of a low-frequency magnetic measurement system. The coil was produced using PCB technology to provide mechanical stability and easy integration close to the magnetic sensors. The transducer design strategy relies on an inverse boundary element method, which has been efficiently adapted to produce optimal multilayer PCB coils subjected to different geometrical and performance constraints. The resulting coil transducer was simulated and experimentally validated under realistic conditions where the payload is magnetically shielded from low-frequency fluctuations by using a three-layer cylindrical mu-metal enclosure. The results show that the specific transducer coil proposed efficiently produces stable magnetic conditions for adequate validation of the magnetic diagnostic system while providing reduced power dissipation and optimal mechanical stability.

Fast-Locking Burst-Mode Clock and Data Recovery for Parallel VCSEL-Based Optical Link Receivers

A burst-mode clock-and-data-recovery (CDR) system for a multi-channel vertical-cavity surface-emitting laser (VCSEL)-based non-return-to-zero (NRZ) optical link’s quarter-rate receivers is presented, that utilizes proxy timing recovery for fast turn-on time. The proxy timing recovery scheme takes advantage of correlated data jitter over parallel optical lanes typically deployed in a data center. Rapid timing recovery of the burst-mode channel is enabled by incrementing/decrementing its phase rotator (PR) control code during idle periods using phase updates from an always-active channel in the link. This work also presents circuit-design techniques to reduce power dissipation during idle times while still enabling fast turn-on time. Simulated in 65 nm CMOS technology, the proposed CDR consumes only 19.5 mW per channel while operating at 10 Gbps/ch and 0.58 mW during its idle-state. Simulation results are presented for the turn-on time with the proposed technique and compared against the turn-on time of a conventional receiver. The proposed technique allows the CDR to lock within 26 unit intervals (UIs) from when it is powered on irrespective of a 1000 ppm frequency offset between the incoming data and the CDR’s reference clock. The complete CDR of each channel occupies an area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed scheme introduces only 1.3 % of area and 2.6 % of on-state power overhead while reducing idle-time power dissipation by 97 %.

Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications

Low Power circuits play a significant role in designing large-scale devices with high energy and power consumption. Adiabatic circuits are one such energy-saving circuits that utilize reversible power. Several methodologies used previously infer the use of CMOS circuits for reducing power dissipation in logic circuits. However, CMOS devices hardly manage in maintaining their performance when it comes to fast switching networks. Adiabatic technology is employed to overcome these difficulties, which can further scale down the dissipation of power by charging and discharging. An Efficient Charge Recovery Logic (ECRL) based adiabatic technology is used here to evaluate arithmetic operations in circuits like inverter, full adder, Carry Look-Ahead adder etc. A better chance at reducing delay in digital circuits is illustrated by developing a Kogge-stone Adder, built using the ECRL technology. The developed circuitry is further integrated into a Fast Fourier Transform (FFT), which demonstrates the circuit’s enhancement into DSP applications. Not only does this design reduce delay in VLSI switching circuits, but also narrows the power dissipation down to a minimum. This technique proved superior to the existing PFAL technique by demonstrating almost 10% less power dissipation with minimal propagation delay. All the circuits have been simulated at 45 nm technology using the Tanner EDA tool.

Multi-Channel, Actively Shielded, Power Efficient MRI Z-Gradient Cylindrical Coil Design Using Target-Field Method

Gradient coils are essential for MRI where fast and large electrical current pulses are typically applied to conventional, single-channel gradient coils, particularly for high-performance gradient applications. However, these pulses result in significant power losses and heating of the coil. We investigate the design of power-efficient multi-channel Z-gradient coils operating in the conventional mode comparing them to conventional single-channel coils designed using similar dimensions and alike DC performance characteristics. The power-efficiencies of thirteen different two-channel configurations having various section lengths for two different dimensions are analyzed. The current density of each section is approximated by Fourier series expansion where a linear equation relating the desired target field and current density is formulated and then solved. A stream function is derived from the obtained current density and then used to extract the final winding patterns of each section using a particular track width and a specific number of turns. The design process involves optimizing the current driving each channel, the distribution of coil windings, and the section size. Similarly, the performance of three-channel coils is also investigated. Results show that a power dissipation reduction of 17-28% and ~23% can be achieved using two- and three-channel coils, respectively. Moreover, we showed that multi-channel coils may have a slightly better shielding efficiency compared to conventional coils. A new methodology for designing two- and three-channel coils is presented where an advantage in terms of power efficiency can be gained depending on design parameters, coil’s dimensions, number of turns, and other metrics.

RETRACTED: Design of 8-bit Dynamic CMOS Priority Resolvers based on Active- High and Active-Low Logic

A couple of new dynamic CMOS based designs of an 8-bit priority resolver corresponding to activehigh and active-low logic are presented in this paper. The proposed designs result from modifications to an 8- bit priority resolver designed by Huang and Chang [15], which pertains to active-high logic. Compared to Huang and Chang’s original 8-bit CMOS priority resolver, the modified designs achieve 4× mean reduction in power dissipation, and report average improvement in the power-delay product by 43%. The simulation results were obtained using Tanner tools (TSPICE), and correspond to a 0.25μm CMOS process technology.

Power optimization of binary division based on FPGA

In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.