Reduce Hardware Cost Research Articles

An Overall Linearized Modeling Method and Associated Delay Time Model for the PV System

There are some significant nonlinearity and delay issues in photovoltaic (PV) system circuits. Therefore, it is very difficult for the existing classic linear control theories to be used in PV systems; this hinders the design of the optimal energy dispatch by considering real-time generation power forecasting methods. To solve this problem, an overall linearized model with variable weather parameters (OLM-VWP) of the PV system is proposed on the basis of small-signal modeling. Meanwhile, a corresponding simplified overall linearized model with variable weather parameters (SOLM-VWP) is presented. The SOLM-VWP avoids analyzing delay characteristics of the complex high-order PV system. Moreover, it can reduce hardware cost and computation time, which makes analysis of the transient performance index of the PV system more convenient. In addition, on the basis of the OLM-VWP and SOLM-VWP, a delay-time model with variable weather parameters (DTM-VWP) of the PV system is also proposed. The delay time of the system can be accurately calculated using the DTM-VWP, and it provides a preliminary theoretical basis for carrying out real-time energy scheduling of the PV system. Finally, simulations are implemented using the MATLAB tool, and experiments are conducted. The results verify that the proposed linearization model of the PV system is accurate and reasonable under varying irradiance and temperature conditions. Meanwhile, the results also verify that the proposed SOLM-VWP and DTM-VWP of the PV system are feasible. Additionally, the results show that some transient performance indexes (delay time, rise time, settling time, and peak time) can be solved by means of equations when the circuit parameters and real-time weather parameters are given.

Cellular automata imbedded memristor-based recirculated logic in-memory computing

Memristor-based circuits offer low hardware costs and in-memory computing, but full-memristive circuit integration for different algorithm remains limited. Cellular automata (CA) has been noticed for its well-known parallel, bio-inspired, computational characteristics. Running CA on conventional chips suffers from low parallelism and high hardware costs. Establishing dedicated hardware for CA remains elusive. We propose a recirculated logic operation scheme (RLOS) using memristive hardware and 2D transistors for CA evolution, significantly reducing hardware complexity. RLOS’s versatility supports multiple CA algorithms on a single circuit, including elementary CA rules and more complex majority classification and edge detection algorithms. Results demonstrate up to a 79-fold reduction in hardware costs compared to FPGA-based approaches. RLOS-based reservoir computing is proposed for edge computing development, boasting the lowest hardware cost (6 components/per cell) among existing implementations. This work advances efficient, low-cost CA hardware and encourages edge computing hardware exploration.

Area-Efficient digital filtering based on truncated multiply-accumulate units in residue number system [formula omitted

High resource consumption of digital filtering devices is one of the main practical problems of digital signal processing. Parallel data processing is one of the most effective approaches to improve the quantitative characteristics of such devices. This paper proposes a method for filtering signals using Truncated Multiply-and-Accumulate units (TMAC) in the residue number system (RNS) using moduli of a special type 2n-1,2n,2n+1. These moduli reduced hardware costs and power consumption compared to state-of-the-art approaches for a 32-bit RNS filter by up to 23% and up to 22.3%, respectively, with a delay increase of 131%. The proposed approach allowed to reduce the device area by up to 14% with comparable energy expended for a 48-bit RNS filter, but the device delay increased by 81%. The results obtained open up the possibility of creating area-efficient and power-efficient devices.

Decompressor for hardware applications

The use of lossless compression in the application specific computers provides such advantages as minimized amount of memory, increased bandwidth of interfaces, reduced energy consumption, and improved self-testing systems. The article discusses known algorithms of lossless compression with the aim of choosing the most suitable one for implementation in a hardware-software decompressor. Among them, the Lempel-Ziv-Welch (LZW) algorithm makes it possible to perform the associative memory of the decompressor dictionary in the simplest way by using the sequential reading the symbols of the decompressed word. The analysis of the existing hardware implementations of the decompressors showed that the main goal in their development was to increase the bandwidth at the expense of increasing hardware costs and limited functionality. It is proposed to implement the LZW decompressor in a hardware module based on a microprocessor core with a specialized instruction set. For this, a processor core with a stack architecture was selected, which is developed by the authors for the tasks of the file grammar analyzing. Additional memory block for the dictionary storing and an input buffer which converts the byte stream of the packed file into a sequence of unpacked codes are added to it. The processor core instruction set is adjusted to both speed up decompression and reduce hardware costs. The decompressor is described by the Very high-speed integral circuit Hardware Description Language and is implemented in a field programable gate array (FPGA). At a clock frequency of up to two hundred megahertz, the average throughput of the decompressor is more than ten megabytes per second. Because of the hardware and software implementation, an LZW decompressor is developed, which has approximately the same hardware costs as that of the hardware decompressor and has a lower bandwidth at the costs of flexibility, multifunctionality, which is provided by the processor core software. In particular, a decompressor of the Graphic Interchange Format files is implemented on the basis of this device in FPGA for the application of dynamic visualization of patterns on the embedded system display

Design and Performance Analysis of Wireless Legitimate Surveillance Systems With Radar Function

Integrated sensing and communication (ISAC) has recently been considered as a promising approach to save spectrum resources and reduce hardware cost. Meanwhile, as information security becomes increasingly more critical issue, government agencies urgently need to legitimately monitor suspicious communications via proactive eavesdropping. Thus, in this paper, we investigate a wireless legitimate surveillance system with radar function. We seek to jointly optimize the receive and transmit beamforming vectors to maximize the eavesdropping success probability which is transformed into the difference of signal-to-interference-plus-noise ratios (SINRs) subject to the performance requirements of radar and surveillance. The formulated problem is challenging to solve. By employing the Rayleigh quotient and fully exploiting the structure of the problem, we apply the divide-and-conquer principle to divide the formulated problem into two subproblems for two different cases. For the first case, we aim at minimizing the total transmit power, and for the second case we focus on maximizing the jamming power. For both subproblems, with the aid of orthogonal decomposition, we obtain the optimal solution of the receive and transmit beamforming vectors in closed-form. Performance analysis and discussion of some insightful results are also carried out. Finally, extensive simulation results demonstrate the effectiveness of our proposed algorithm in terms of eavesdropping success probability.

An Efficient Algorithm-Hardware Co-Design for Radar-Based Fall Detection With Multi-Branch Convolutions

In this paper, we propose an efficient algorithm-hardware co-design framework to realize radar-based fall detection with limited resources. We first design a compact neural network model named MB-Net with multi-branch convolutions for feature extraction of radar time series data combined with multi-scale wavelet transform. After that, an FPGA-based neural network (NN) accelerator tailored for the proposed network is designed. The proposed NN accelerator replaces the general multipliers with non-exact multipliers to reduce the hardware cost. For the multi-branch convolution layer, a novel layer computing sequence is introduced to improve the efficiency of the processing element (PE) array and reduce the memory footprint. In addition, the average pooling operation in the proposed network is folded into the quantization factors to reduce hardware cost. The experimental findings show that the MB-Net can maintain competitive performance in comparison to state-of-the-art methods while the hardware cost is significantly lower. The proposed network model is implemented in Zynq ZC702 board using only 3615 LUTs, 1843 FFs, 11.5 BRAMs, and 8 DSPs with 0.234 W power consumption. Through algorithm and hardware co-optimization, the fall detection accelerator can achieve 95% PE efficiency and takes 0.346 ms latency for a radar sample interference with only 80.96 uJ energy consumption.

Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.

Probabilistic Classification Method of Spiking Neural Network Based on Multi-Labeling of Neurons

Recently, deep learning has exhibited outstanding performance in various fields. Even though artificial intelligence achieves excellent performance, the amount of energy required for computations has increased with its development. Hence, the need for a new energy-efficient computer architecture has emerged, which further leads us to the neuromorphic computer. Although neuromorphic computing exhibits several advantages, such as low-power parallelism, it exhibits lower accuracy than deep learning. Therefore, the major challenge is to improve the accuracy while maintaining the neuromorphic computing-specific energy efficiency. In this paper, we propose a novel method of the inference process that considers the probability that after completing the learning process, a neuron can react to multiple target labels. Our proposed method can achieve improved accuracy while maintaining the hardware-friendly, low-power-parallel processing characteristics of a neuromorphic processor. Furthermore, this method converts the spike counts occurring in the learning process into probabilities. The inference process is conducted to implement the interaction between neurons by considering all the spikes that occur. The inferring circuit is expected to show a significant reduction in hardware cost and can afford an algorithm exhibiting a competitive computing performance.

3-D Hybrid Beamforming for Terahertz Broadband Communication System With Beam Squint

In this paper, the three-dimensioned (3D) hybrid beamforming is designed for the terahertz (THz) based broadband broadcasting communication system with beam squint. Specifically, the full-dimensional THz massive multiple input multiple output (M-MIMO) channel model and the array gain of the uniform planar array (UPA) are first analyzed in the context of the beam squint effect. Then, a 3D hybrid beamforming architecture is proposed by leveraging two-tier true time delay (TTD), which is able to combat the beam squint effect from the horizontal and vertical directions. To further reduce hardware cost and power consumption, a low-cost 3D hybrid beamforming architecture with a two-tier TTD and phase shifter combination (TPC) is designed. Simulation results are shown that the performance of the proposed 3D hybrid beamforming architectures is capable of approaching that of the full-digital beamforming counterpart in the face of beam squint, despite relying on reduced implementation cost.

All-digital transmit beamformer for portable high-frequency ultrasound imaging systems.

To meet the requirements of high-frequency ultrasound imaging systems, a transmit-beamforming integrated circuit with higher delay resolution than conventional transmit-beamforming circuits, which are typically implemented using field-programmable gate array chips, is presented. It also requires smaller volumes, allowing for portable applications. Its proposed design includes two all-digital delay-locked loops providing a specified digital control code for a counter-based beamforming delay chain (CBDC) to generate stable and suitable delays for exciting the array transducer elements without variations in process, voltage, and temperature. Moreover, to maintain the duty cycle of long propagation signals, this novel CBDC requires only a few delay cells, significantly reducing hardware costs and power consumption. Simulations were conducted, revealing a maximum time delay of 451.9ns with a time resolution of 652ps and a maximum lateral resolution error of 0.04mm at 6.8mm.

METHODICAL APPARATUS FOR PROTECTING AGAINST ERRORS OF PROCESSOR OF SPECIALIZED COMPUTERS

An analysis of methods for detecting and correcting errors in specialized computers has been carried out, which shows that the most effective methods for detecting and correcting errors are corrective codes with syndromic decoding, which allows solving this problem using 10…30 % of hardware costs for these purposes. The possibility of using corrective codes to control the processor when performing arithmetic and logical operations, with the exception of the logical negation operation, has been established. The necessity of controlling the negation operation when constructing an additional code is substantiated, since when it is formed, the values of information bits are first inverted, and one is added to the result obtained. The two’s complement code is used to correct the result of the product when the signs of the multiplicand and the multiplier differ. The division operation is carried out by repeatedly subtracting the divisor from the dividend (adding the dividend to the divisor presented in the additional code). An example of using a Hamming code to correct processor errors during an addition operation is considered. It is shown that the existing algebraic codes cannot be used to control the arithmetic operations of subtraction and division, since they do not allow controlling the logical inversion operation necessary to represent a negative number in an additional code. An algorithm for constructing a code has been developed that makes it possible to control the logical operation of negation and, consequently, the representation of a negative number in an additional code. The parameters of the developed code are determined. A methodical apparatus for detecting and correcting processor errors when performing arithmetic operations of multiplication and division is proposed. An example of using the proposed code to control the arithmetic operation of subtraction is considered. In contrast to the methods of using codes to control the arithmetic operation of addition, the proposed code allows you to control the formation of an additional code to detect and correct errors when performing a subtraction (division) operation. The use of the proposed method makes it possible to significantly reduce hardware costs for detecting and correcting errors in a computer.

First Superferromagnetic Remanence Characterization and Scan Optimization for Super-Resolution Magnetic Particle Imaging.

Magnetic particle imaging (MPI) is a sensitive, high-contrast tracer modality that images superparamagnetic iron oxide nanoparticles, enabling radiation-free theranostic imaging. MPI resolution is currently limited by scanner and particle constraints. Recent tracers have experimentally shown 10× resolution and signal improvements with dramatically sharper M-H curves. Experiments show a dependence on interparticle interactions, conforming to literature definitions of superferromagnetism. We thus call our tracers superferromagnetic iron oxide nanoparticles (SFMIOs). While SFMIOs provide excellent signal and resolution, they exhibit hysteresis with non-negligible remanence and coercivity. We provide the first quantitative measurements of SFMIO remanence decay and reformation using a novel multiecho pulse sequence. We characterize MPI scanning with remanence decay and coercivity and describe an SNR-optimized pulse sequence for SFMIOs under human electromagnetic safety limitations. The resolution from SFMIOs could enable clinical MPI with 10× reduced scanner selection fields, reducing hardware costs by up to 100×.

Machine learning assisted LEDs combination selection and user matching of RISs enabled GSSK-VLC system

To improve the performance of indoor generalized space shift keying (GSSK) visible light communication (VLC) system, multiple reconfigurable intelligent surfaces (RISs) enabled user matching and light emitting diodes (LEDs) combination selection approach is proposed. Firstly, the multiple RISs enabled GSSK-VLC system model is provided, which arranges multiple RISs to realize the full coverage of the service area in an indoor space. Then, based on received power, the special user is readily matched to the corresponding RIS. Finally, machine learning enabled LEDs combination selection techniques are exploited to reduce hardware costs and improve system bit error rate (BER) performance, wherein the machine learning approaches considered include k-nearest neighbor (k-NN), support vector machine (SVM), Naive Bayes (NB), and back propagation neural network (BPNN). Among these LEDs combination selection approaches, the BPNN has the best BER performance for the highest classification accuracy. Simulation results show that the proposed joint user-RIS matching and LEDs combination selection scheme can achieve better BER performance and reduce system complexity effectively.

Research on MMC Improved Sub-Module Topology With DC Fault Ride-Through and Negative Level Output Capability

Modular multilevel converter (MMC) is a modern and preferred topology among the voltage source converters (VSCs) in high voltage direct current (HVdc) transmission. However, the traditional half-bridge sub-module (SM) cannot block the dc fault current. Hence, the novel SM topology with dc fault ride-through capability is introduced. This article proposes an improved diode-clamp SM (IDCSM) structure. Based on the DCSM topology, the two capacitors’ connection in the IDCSM is modified to operate independently and generate output voltage levels of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- u_{c}$ </tex-math></inline-formula> , 0, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$u_{c}$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2u_{c}$ </tex-math></inline-formula> based on the additional switching devices. The IDCSM with dc fault ride-through and negative level output capability can increase the number of output levels and significantly reduce hardware cost. In addition, this article adopts an equivalent half-bridge modulation (EHBM) strategy that can modulate all the MMC SM topologies with the comparison algorithm, simplifying the complicated logic calculation process. Then the IDCSM power loss, cost, and dc fault ride-through characteristics are illustrated in detail. Finally, the simulation and experimental results verify the feasibility of the proposed IDCSM topology and EHBM.

Remote Phase-Shift LiDAR With Communication

The integrated sensing and communication is emerging as a crucial technology due to reduced hardware costs and broad application scenarios. However, there is a contradiction between ranging and communication in phase-shift light detection and ranging (LiDAR) for the utilization of the subcarrier’s phase. A scheme called phase-shift laser ranging with communication (PLRC) is proposed to enable both ranging and communication using the same transmitted signal in this paper. The message encoded with pseudo-random noise code is modulated into the phase of the subcarrier for laser emission, and thus the received signal carries the data and the phase difference due to the distance. The received signal is subject to correlation, waveform recovery, and phase-shift measurement with the local signal at the LiDAR transceiver, and the distance is derived from the complete phase to avoid range ambiguity. The data is extracted from the spread spectrum signal at the communication receiver. The performance in terms of the measured distance and precision of LiDAR, the bit error rate of communication is obtained for the proposed solution. Meanwhile, the optimized light ratio for ranging and communication is derived. The experimental demonstration is carried out, the range precision is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.54\,\,{\times }\,\,10^{-3}$ </tex-math></inline-formula> m, and the communication capability meets 1.43 Mbit/s.

FPGA Implementation of a Real-Time Edge Detection System Based on an Improved Canny Algorithm

Canny edge detection is one of the most widely used edge detection algorithms due to its superior performance. However, it is a complex, time-consuming process and has a high hardware cost. To overcome these issues, an improved Canny algorithm is proposed in this paper. It uses the Sobel operator and approximation methods to calculate the gradient magnitude and direction for replacing complex operations with reduced hardware costs. Otsu’s algorithm is introduced to adaptively determine the image threshold. However, Otsu’s algorithm has division operations, and the division operation is complex and has low efficiency and slow speed. We introduce a logarithmic unit to turn the division into a subtraction operation that is easy to implement by hardware but does not affect the selection of the threshold. Experimental results show that the system can detect the edge of the image well without adjusting the threshold value when the external environment changes and requires only 1.231 ms to detect the edges of the 512 × 512 image when clocked at 50 MHz. Compared with existing FPGA implementations, our implementation uses the least amount of logical resources. Thus, it is more suitable for platforms that have limited logical resources.

Hybrid interconnection networks for reducing hardware cost and improving path diversity based on fat‐trees and hypercubes

AbstractFat‐tree topologies are widely used in interconnect network designs for parallel supercomputers. In the classic fat‐tree, compute nodes are connected to leaf stage switches by links. Given a large number of compute nodes, many switches and links are required, resulting in high hardware costs. To solve this problem, this paper proposes two hybrid topologies, ‐Cube ‐Ary ‐Tree (CAT) and Mirrored ‐Cube ‐Ary ‐Tree (MiCAT), based on fat‐tree and hypercube. Instead of connecting compute nodes directly to a leaf switch, we connect a ‐cube to the switch, and each switch in the ‐cube part connects compute nodes. That is, this ‐cube consists of switches and compute nodes. We give the shortest path routing algorithms and evaluate the path diversity, cost, performance, and average packet latency of CAT and MiCAT. The results show that CAT and MiCAT can save up to switches and links in a large‐scale parallel system, for example, compared to fat‐trees, and meanwhile, both CAT and MiCAT have higher path diversities than fat‐trees.

Hybrid Beamforming for Dual Functioning Multi-input Multi-output Radar using Dimension Reduced-baseband Piecewise Successive Approximation

A reliable and effective hybrid beamforming design for dual functioning multi-input multi-output (MIMO) radar is a challenging research problem because of the concerns related to limited user capacity, interference, and lack of performance trade-off. Due to the shortage of available spectrum, radar frequency spectrum sharing has become vital in emerging 5G communication systems. This will reduce spectrum congestion, therefore receiving significant attention. The existing hybrid beamforming methods reduce the radio frequency (RF) chains but improving user capacity is still a major concern. Future dual radar-communication designs are having challenges in enhancing the user capacity with minimum RF chains, interference mitigation, and hardware cost reduction. This work proposes a novel approach to a hybrid beamforming mechanism for dual-functioning MIMO radar. This mechanism uses the dimension-reduced baseband piecewise successive approximation integrated with a digital precoder. At the analog precoder, the piecewise successive iterative approximation approach is applied to perform the analog beamforming. The novel hybrid beamforming with lens antenna array integration improves the user capacity and reduces power requirement, interference, and expenses. The simulation results showed improved performances compared to existing state-of-the-art methods in terms of bit error rate, spectral efficiency, energy efficiency, and response time.

Автоматическое построение отказоустойчивых бортовых сетей

Fault tolerance is one of the key issues for on-board networks of autonomously operating vehicles. The number of devices in such networks is increasing; there is a need for methods for automating the design of networks, taking into account the required fault tolerance and technical limitations. Purpose: the purpose of the study is the implementation of methods and algorithms that contribute to the assessment of the fault tolerance of on-board networks, as well as the automatic generation of network structures with the required fault tolerance. Methods: The obtained methods and algorithms are based on the elements of graph theory, in particular – estimation of connectivity and shortest path search. The graphs are compiled based on the structure of the onboard network using a number of proposed rules. Structural redundancy is considered as a method of ensuring fault tolerance. The developed method provides reasonable addition of the network elements, in contrast to the often used copying of the network structure. The method consists of two stages: the new network structure is generated according to the required fault tolerance, and then iteratively refines the network structure in order to reduce hardware costs. Results: the use of the developed method simplifies and speeds up the design of on-board networks, since a formalized assessment of such a network is carried out at the design stage, before its actual assembly. The process of achieving of the required fault tolerance for large network structures takes less than a minute. Practical relevance: the presented method is implemented within the framework of the computer-aided system for design and modeling of onboard networks, a longterm approbation was carried out as part of real projects for the development of onboard networks of spacecraft. Discussion: there are no analogues of such a software implementation for on-board networks. The solutions obtained using the method in practice proved to be close to optimal; the research results have positive feedback from specialists.

Dual-Bit-Wise Stochastic Decoding for Polar Codes

Polar codes, being the first class of codes with provable capacity-achieving property, have aroused extensive attention. The belief propagation (BP) algorithm, which is one of the popular decoding approaches for polar codes, possesses inherent high parallelism but also high computational complexity. With low complexity and high fault tolerance, stochastic computing has been well studied and applied to BP decoding for polar codes. However, existing stochastic BP decoders suffer from high decoding latency. In this paper, firstly, a novel dual-bitwise iterative message update method is proposed for stochastic BP, reducing the decoding latency by more than half. Based on the dual-bit-wise decoding, more special nodes in the factor graph are investigated and then fully exploited to pursue lower decoding complexity than prior arts. Moreover, a well-optimized architecture is developed for the proposed stochastic decoder, where the random number generator (RNG), tracking forecast memory (TFM), and hard decision unit are intelligently designed for reduced hardware cost. Experimental results demonstrate that the presented decoder can exhibit 61.7% lower decoding latency than the state-of-the-art works. Besides, the throughput and hardware efficiency can be improved by nearly 2.8×, and 2.7×, respectively.