Reduce Hardware Cost Research Articles

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras

In this paper a 4928 × 3264 pixel CMOS image signal processor (ISP) is proposed for digital still cameras with low complexity and high performance. To reduce hardware cost and keep high performance, novel algorithms are proposed to process image signals. Firstly, a joint demosaic and denoise algorithm is presented for both color interpolation and Gaussian noise removal. This novel joint algorithm achieves high performance and saves line buffers. Furthermore, image edge enhancement is performed jointly with this algorithm to save memory cost. Secondly, a low complexity auto white balance hardware architecture is presented based on histogram equalization algorithm. This algorithm can handle some extremely bad scenes. To reduce hardware cost, the contrast enhancement is realized jointly with auto white balance. Thirdly, to remove pulse noise, a high performance and low complexity hardware implementation is proposed based on median filter using only nine comparators. Based on these algorithms and hardware, the VLSI architecture of the ISP is proposed and implemented in a SMIC 65nm CMOS technology. The gate count of the ISP is 158k and core area is 1.5mm2. Only 8 line buffers with total 462 Kb SRAM are used in the ISP. The throughput of the ISP is 12Gb/s with a frequency of 333MHz and power consumption of 77mW.

A cross-layer flow schedule with dynamical grouping for mitigating larger-scale TCP incast

Data center network (DCN), a type of network featuring low delays and high bandwidths, exchanges information rapidly through high-performance network switches. Currently, DCN provides various distributed services to satisfy user requirements. However, the size of buffers in the switches of DCNs is limited, thus causing throughput collapse when transmission control protocol (TCP) is used for multiple-to-one transmissions. Dropped packets result in additional retransmission costs and cause a substantial decrease in the efficient use of network bandwidths. Such a decrease in network performance is called a TCP incast problem. Previous studies have typically focused on modifying the original TCP or increasing additional switch hardware costs; rarely have studies focused on the existing DCN environments. Therefore, this study proposes using a cross-layer flow schedule with dynamical grouping (CLFS-DG) scheme to reduce the effect of TCP incast in DCNs. In CLSF-DG, data transmission schedules are organized by a receiver using application-level information. Multiple data flows are then grouped for simultaneously transmission to improve TCP throughput and satisfy deadline requirements. CLFS-DG can be applied to inexpensive switches without extra hardware support, substantially reducing hardware costs. The simulation result indicated that CLFS-DG can effectively prevent TCP incast occurrence and ensure the quality of service in both local networks and fat-tree topologies typically applied in the DCN. A realistic multiple-to-one transmission in the one-hop local network scenario had been set up and tested. The average error rate of the simulation results and actual experimental results is small and about 4.6%. The results show that CLFS-DG can actually be applied to real large networks.

Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding

Piecewise polynomial interpolation is a well-established technique for hardware function evaluation. The paper describes a novel technique to minimize polynomial coefficients wordlength with the aim of obtaining either exact or faithful rounding at a reduced hardware cost. The standard approaches employed in literature subdivide the design of piecewise-polynomial interpolators into three steps (coefficients calculation, coefficients quantization and arithmetic hardware optimization) and estimate conservatively the overall approximation error as the sum of the error components arising in each step. The proposed technique, using Integer Linear Programming (ILP), optimizes the polynomial coefficients taking into account all error components simultaneously. This gives two advantages. Firstly, we can obtain exactly rounded approximations; secondly, for faithfully rounded interpolators, we avoid any overdesign due to pessimistic assumptions on error components, optimizing in this way the resulting hardware. The proposed ILP based algorithm requires an acceptable CPU time (from few seconds to tens of minutes) and is suited for approximations up to, maximum, 24 input bits. The results compare favorably with previously published data. We present synthesis results in 28 nm and 90 nm CMOS technologies, to further assess the effectiveness of the proposed approach.

Error correction of digital signal processing devices using non-positional modular codes

The paper discusses an algorithm for correcting code errors of the residue number system using a positional characteristic. Application of parallel-pipeline computations of this positional characteristic allows us to reduce hardware costs by 7.2% for processing 2-byte data represented in a residue number system code. The main properties of codes allow us to provide the required fault-tolerance for multi-rate DSP devices. The results provided in the paper can be applied to hydroacoustic monitoring tasks.

Valutazione economica delle tecnologie RFID e open source per la tracciabilità del legno in Calabria

Abstract: The aim of this work was to assess the economic sustainability of the implementation of a wood traceability system in Calabria based on RFID and open source technologies. We identified a break-even point in its implementation under different scenarios in order to highlight the economic sustainability limits, expressed in terms of m3 or tons of processed product. The results showed that the use of RFID technology along the supply chain could lead to an effective operational simplification and to a more efficient use of resources. Based on the average market prices for timber (80-120 € / m3), the implementation of RFID technology led to an increase in timber price by 8% under the worst scenarios. This suggests that the use of open source technologies for wood traceability is already feasible and economically sustainable, as 40% of private companies stated their willingness to pay a premium price (on average 3.25% higher) for purchasing certified local wood products in Calabria. Moreover, we expect a further reduction of tags and hardware costs in the next future, up to half the costs estimated in this work, thus making the application of such technology to timber traceability even more affordable.

NOMA Meets Finite Resolution Analog Beamforming in Massive MIMO and Millimeter-Wave Networks

Finite resolution analog beamforming (FRAB) has been recognized as an effective approach to reduce hardware costs in massive multiple-input multiple-output (MIMO) and millimeter-wave networks. However, the use of FRAB means that the beamformers are not perfectly aligned with the users' channels and multiple users may be assigned similar or even identifical beamformers. This letter shows how non-orthogonal multiple access (NOMA) can be used to exploit this feature of FRAB, where a single FRAB based beamformer is shared by multiple users. Both analytical and simulation results are provided to demonstrate the excellent performance achieved by this new NOMA transmission scheme.

Modulation of a trapezoidal signal: improving signal quality and reducing costs in power inverters

Power inverters applied in industries have seen a growth in modulation techniques over recent years. The aim of modulation techniques is to improve the quality of the inverter output signal and to reduce inverter losses. To improve an output signal, the amplitude of the fundamental frequency should be increased and the harmonics should be reduced. If a modulation technique can achieve these two objectives, a much smaller output filter is required to reduce hardware cost and filter losses. In this study, a technique is proposed where the obtained modulated signal can be directly used without the need of filtering. The resulting frequency profile fulfils the EN50160 standard, which sets the limits for harmonic components to ensure the quality in public low-voltage and medium-voltage power supplies. In addition, the proposed scheme requires a low computational algorithm allowing the use of low-cost microprocessors or Digital Signal Processor (DSPs). The proposed algorithm is based on a simple vector seed, making it possible to obtain all the patterns of Pulse Width Modulation (PWM).

A fault‐tolerant routing strategy for k‐ary n‐direct s‐indirect topologies based on intermediate nodes

SummaryExascale computing systems are being built with thousands of nodes. The high number of components of these systems significantly increases the probability of failure. A key component for them is the interconnection network. If failures occur in the interconnection network, they may isolate a large fraction of the machine. For this reason, an efficient fault‐tolerant mechanism is needed to keep the system interconnected, even in the presence of faults. A recently proposed topology for these large systems is the hybrid k‐ary n‐direct s‐indirect family that provides optimal performance and connectivity at a reduced hardware cost. This paper presents a fault‐tolerant routing methodology for the k‐ary n‐direct s‐indirect topology that degrades performance gracefully in presence of faults and tolerates a large number of faults without disabling any healthy computing node. In order to tolerate network failures, the methodology uses a simple mechanism. For any source‐destination pair, if necessary, packets are forwarded to the destination node through a set of intermediate nodes (without being ejected from the network) with the aim of circumventing faults. The evaluation results shows that the proposed methodology tolerates a large number of faults. For instance, it is able to tolerate more than 99.5% of fault combinations when there are 10 faults in a 3‐D network with 1000 nodes using only 1 intermediate node and more than 99.98% if 2 intermediate nodes are used. Furthermore, the methodology offers a gracious performance degradation. As an example, performance degrades only by 1% for a 2‐D network with 1024 nodes and 1% faulty links.

A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

Low‐Latency SRT Division and Square Root Based on Remainder and Quotient Prediction

Sweeney, Robertson and Tocher (SRT) algorithm is a common and efficient way for division and square root (div/sqrt). We present to overlap two iterations into one cycle by predicting remainder and quotient. To reduce latency, redundant representation is used superiorly, as well as the use of a minimum redundancy factor. Division and square root can be integrated into one unit which causes a reduction in hardware cost. With 40nm technology library, the area of our architecture after layout design, is 37795µm2, the power is 81.19mW and the delay is only 656ps. The cycles for double-precision division and square root are 17 and 16, respectively. Experiments show our architecture achieves small latency and high frequency, together with modest area and power.

Astronomical Image Acquisition Using an Improved Track and Accumulate Method

“Track and Accumulate” (T&A) is an alternative astronomical image capture method where exposures are combined during imaging by aligning on a reference star. The benefit is an increased dynamic range, thus allowing both bright and dim objects to be captured in the same image. The main limitation is that correlated noise from the frames will form squiggles on the combined image as the result of telescope drift, especially when using narrowband filters. In general, the advantages of the T&A method are insufficient to outweigh this limitation, and most astrophotographers prefer to take individual images and combine later. In this paper, several enhancements to the original T&A method are detailed, which improve on the process as well as reduce correlated noise. An algorithm is proposed where most postprocessing is integrated into the T&A procedure. These improvements simplify the imaging process, reduce hardware costs, and lower the technical bar for producing quality astronomical photos. The algorithm has been field tested on a variety of astronomical objects, and the resultant images are as good as those produced by the traditional method, yet require less imaging and processing time.

An Optimal Method for Sensorless Control of DFIG based WECS using PSO

Objectives: A sensorless method is employed to control real and reactive power for DFIG in an optimal way under various load conditions. The main objective of this paper is to maintain constant voltage and constant frequency. Method/Analysis: In this paper, a sensorless control technique with the optimal Proportional-Integral (PI) controller parameters of a test system using Particle Swarm Optimization (PSO) is explained. The techniques for the development of sensorless drives are: reduction of hardware complexity and cost, decreased maintenance requirements, elimination of sensor cables. Optimal tuning of PI controller parameters gives high quality solution. Findings: The system performance with PI controller parameters and PSO tuned PI controller parameters are compared. MATLAB software is used to develop the simulation and the results are presented. Applications: Low Voltage Ride Through, Lvrt, OFFSHORE wind farms.

Area-Efficient Scaling-Free DFT/FFT Design Using Stochastic Computing

Discrete Fourier transform (DFT) is an important transformation technique in signal processing tasks. Due to its ultrahigh computing complexity as $O(\!N^{\!2}\!)$ , $N$ - point DFT is usually implemented in the format of fast Fourier transformation (FFT) with the complexity of $O(N\log N)$ . Despite this significant reduction in complexity, the hardware cost of the multiplication-intensive $N$ - point FFT is still very prohibitive, particularly for many large-scale applications that require large $N$ . This brief, for the first time , proposes high-accuracy low-complexity scaling-free stochastic DFT/FFT designs. With the use of the stochastic computing technique, the hardware complexity of the DFT/FFT designs is significantly reduced. More importantly, this brief presents the scaling-free stochastic adder and the random number generator sharing scheme, which enable a significant reduction in accuracy loss and hardware cost. Analysis results show that the proposed stochastic DFT/FFT designs achieve much better hardware performance and accuracy performance than state-of-the-art stochastic design.

Reduction of hardware costs in the implementation of a Moore FSM circuit on hybrid FPGA

In this paper a method to reduce hardware costs in Moore FSM circuit in the implementation on hybrid FPGA is proposed. The method uses features of Moore FSM and elemental basis of FPGA, and it is based on the use of two sources of classes of pseudoequivalent states due to the large number of inputs of built-in PLA elements in modern hybrid FPGA. Figs.: 3. Refs.: 17 titles.Keywords: reduction of hardware costs; Moore FSM; hybrid FPGA; pseudoequivalent states; PLA elements.

Low‐cost multi‐standard video transform core using time‐distribution scheme

Cost-effective two-dimensional (2D) discrete cosine transform (DCT) and inverse DCT architectures capable of supporting multiple standards of MPEG, H.264 and VC-1 are presented. The proposed core utilises a 1D core and a transposed memory to achieve a low cost design. Multi-level factor share is implemented in conjunction with distributed arithmetic in a system to enable the sharing of the coefficient matrix circuit in order to reduce hardware costs. The proposed approach employs a time-distribution scheme to enable the simultaneous processing of the first and second dimensions to enhance throughput. A high efficiency of this approach was verified by fabricating a test chip using the TSMC 0.18 μm CMOS process. The architecture has an operating frequency of 200 MHz, and throughput of 800 M-pixels/s with a gate count of 44.5 K.

Configurable Floating‐Point FFT Accelerator on FPGA Based Multiple‐Rotation CORDIC

Fast Fourier transform (FFT) accelerator and Coordinate rotation digital computer (CORDIC) algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmented-parallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to 8192 points, occupies 33230(3%) REGs and 143006(30%) LUTs. The clock frequency can reach 122MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What's more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.

Development of a surrogate-based vehicle dynamic model to reduce computational delays in a driving simulator

The development of a real-time driving simulator involves highly complex integrated and interdependent subsystems that require a large amount of computational time. When advanced hardware is unavailable for economic reasons, achieving real-time simulation is challenging, and thus delays are inevitable. Moreover, computational delays in the response of driving simulator subsystems reduce the fidelity of the simulation. In this paper, we propose a technique to decrease computational delays in a driving simulator. We used approximation techniques, sensitivity analysis, decomposition, and sampling techniques to develop a surrogate-based vehicle dynamic model (SBVDM). This global surrogate model can be used in place of the conventional vehicle dynamic model to reduce the computational burden while maintaining an acceptable accuracy. Our results showed that the surrogate model can significantly reduce computing costs compared to the computationally expensive conventional model. In addition, the response time of the SBVDM is nearly five times faster than the original simulation codes. Also, as a method to reduce hardware cost, the SBVDM was used and the results showed that most of the responses were accurate and acceptable in relation to longitudinal and lateral dynamics. Based on the results, the authors suggested that the proposed framework could be useful for developing low-cost vehicle simulation systems that require fast computational output.

Large Array Null Steering Using Compressed Sensing

In this letter, array null steering is formulated as a sparse recovery problem. In addition, a novel null steering scheme for large arrays by perturbing only a few elements is presented. To achieve this goal, compressed sensing (CS) is used to exploit the sparsity of the perturbed elements. The advantages of the proposed scheme are a significant reduction in hardware cost and lower power consumption, as well as less aging of the elements and faster response. Simulation results show that the CS-based method could be efficiently used to generate wide nulls using at least two elements. The interference rejection ratio achieved by the proposed method is 10–20 dB better than the existing solutions. The performance of different null generation methods in terms of peak-to-sidelobe ratio, pointing error, and beam-width is compared as well. The proposed algorithm is a prominent solution for the future 5G base stations, where a fast and low-cost beam shaping algorithm is required.

Sparse Arrays and Sampling for Interference Mitigation and DOA Estimation in GNSS

This paper establishes the role of sparse arrays and sparse sampling in antijam global navigation satellite systems (GNSS). We show that both jammer direction of arrival estimation methods and mitigation techniques benefit from the design flexibility of sparse arrays and their extended virtual apertures or coarrays. Taking advantage of information redundancy, significant reduction in hardware and computational cost materializes when selecting a subset of array antennas without sacrificing jammer nulling or localization capabilities. In addition to the spatial array sparsity, antijam can utilize sparsity of jammers in the spatio–temporal frequency domains. By virtue of their finite number, jammers in the field of view are sparse in the azimuth and elevation directions. For the class of frequency modulated jammers, sparsity is also exhibited in the joint time-frequency signal representation. These spatial and signal characteristics have called for the development of sparsity-aware antijam techniques for the accurate estimation of jammer space-time-frequency signature, enabling its effective sensing and excision. Both theory and simulation examples demonstrate the utility of coarrays, sparse reconstructions, and antenna selection techniques for antijam GNSS.

First successful satellite laser ranging with a fibre-based transmitter

Satellite laser ranging (SLR) is an established technology used for geodesy, fundamental science and precise orbit determination. This paper reports on the first successful SLR measurement from the German Aerospace Center research observatory in Stuttgart. While many SLR stations are in operation, the experiment described here is unique in several ways: The modular system has been assembled completely from commercial off-the-shelf components, which increases flexibility and significantly reduces hardware costs. To our knowledge it has been the first time that an SLR measurement has been conducted using an optical fibre rather than a coudé path to direct the light from the laser source onto the telescope. The transmitter operates at an output power of about 75mW and a repetition rate of 3kHz, and at a wavelength of 1064nm. Due to its rather small diameter of only 80μm, the receiver detector features a low noise rate of less than 2kHz and can be operated without gating in many cases. With this set-up, clear return signals have been received from several orbital objects equipped with retroreflectors. In its current configuration, the system does not yet achieve the same performance as other SLR systems in terms of precision, maximum distance and the capability of daylight ranging; however, plans to overcome these limitations are outlined.