Hardware Efficient Reconfigurable Digital Down Converter for Software Radio Receiver

Abstract

ABSTRACT This paper describes a reconfigurable digital down converter (DDC) that can reduce the input sampling frequency from 128 MHz to an output of 1 MHz on a field-programmable gate array (FPGA) device. The proposed design employs a polyphase mixer followed by a half-band (HB) filter and a finite impulse response (FIR) filter. All the decimation filters involve polyphase architectures, enabling efficient hardware implementation. The polyphase mixer can reduce the high sampling rate frequency, and combining both HB and FIR filters results in a complex down-converted baseband spectrum. In addition, the modified HB filter reduces multiplier units, and the proposed FIR filter saves the delay elements. Using the optimal hardware description language (HDL) programming style, the design can further improve the area efficiency without sacrificing functionality. To evaluate the performance, the design has been implemented on the Kintex-7 Xilinx FPGA device. Experimental outcomes show that the proposed design significantly reduces hardware costs associated with other existing designs. Finally, a verification test certifies that the DDC has achieved a satisfactory spurious-free dynamic range (SFDR) of 115 dB. The high sampling rate and parallel processing capabilities of the proposed DDC make it an attractive solution for any software radio standard.