METHODICAL APPARATUS FOR PROTECTING AGAINST ERRORS OF PROCESSOR OF SPECIALIZED COMPUTERS

Abstract

An analysis of methods for detecting and correcting errors in specialized computers has been carried out, which shows that the most effective methods for detecting and correcting errors are corrective codes with syndromic decoding, which allows solving this problem using 10…30 % of hardware costs for these purposes. The possibility of using corrective codes to control the processor when performing arithmetic and logical operations, with the exception of the logical negation operation, has been established. The necessity of controlling the negation operation when constructing an additional code is substantiated, since when it is formed, the values of information bits are first inverted, and one is added to the result obtained. The two’s complement code is used to correct the result of the product when the signs of the multiplicand and the multiplier differ. The division operation is carried out by repeatedly subtracting the divisor from the dividend (adding the dividend to the divisor presented in the additional code). An example of using a Hamming code to correct processor errors during an addition operation is considered. It is shown that the existing algebraic codes cannot be used to control the arithmetic operations of subtraction and division, since they do not allow controlling the logical inversion operation necessary to represent a negative number in an additional code. An algorithm for constructing a code has been developed that makes it possible to control the logical operation of negation and, consequently, the representation of a negative number in an additional code. The parameters of the developed code are determined. A methodical apparatus for detecting and correcting processor errors when performing arithmetic operations of multiplication and division is proposed. An example of using the proposed code to control the arithmetic operation of subtraction is considered. In contrast to the methods of using codes to control the arithmetic operation of addition, the proposed code allows you to control the formation of an additional code to detect and correct errors when performing a subtraction (division) operation. The use of the proposed method makes it possible to significantly reduce hardware costs for detecting and correcting errors in a computer.