Estimation of hardware and time redundancy when using an additive error vector to correct burst errors in digital data transmission systems

Abstract

In digital data transmission systems, to improve noise immunity, cyclic codes are widely used, detecting and correcting byte (packet) errors. An error packet is understood to mean errors whose multiplicity does not exceed the number of bits b of the information block. Cyclic codes are used to correct byte errors. The most effective method for correcting byte errors are Reed-Solomon codes, which allow correcting errors in a given number of bytes of information. The main problem of using cyclic (sequential) codes is a long delay time associated with the need to perform a division operation to obtain the remainder, which is not acceptable for digital data transmission systems operating in real time. For example, when using the Reed-Solomon code with a code set length of 69 information bits, the implementation of decoding according to the Euclidean algorithm requires 96 clock cycles, which cannot ensure the channel operation in real time. To eliminate this drawback, one should use codes that correct burst errors that implement an algebraic coding procedure with syndromic decoding of information. However, replacing the cyclic procedure for encoding (decoding) information with a syndromic one leads to a sharp increase in hardware costs associated with the use of a memory unit in the decoder for storing error vector values and a decoder for generating error addresses in accordance with the resulting syndrome. Thus, there is a need to develop a methodological apparatus associated with the construction of a code that corrects errors in a given number of bytes of information and an estimate of the hardware and time costs associated with this purpose. In this work, the need to develop a methodological apparatus associated with the construction of a code that corrects errors in a given number of bytes of information with algebraic syndromic decoding and an assessment of the hardware and time costs associated with this purpose is substantiated. The paper presents the rules for constructing a correcting code that corrects errors in a given number of bytes of information, which implements a linear procedure for constructing a correcting code with syndromic decoding and using an additive error vector, which made it possible to reduce hardware costs for constructing a decoding device (to reduce the amount of memory for storing error vector values). For the developed method for correcting byte errors, expressions for evaluating the number are obtained: checking discharges; additive error vectors that do not require their storage in a memory block; error vectors, for burst errors that occur in adjacent bytes at the same time and require their values to be stored in a memory block. A comparative assessment of hardware and time redundancy in the implementation of the proposed method for correcting packet errors with existing methods is carried out. The proposed method of error correction in a given number of bytes of information with additive formation of the error vector differs from the existing ones in that it allows: carry out the correction of burst errors with algebraic-syndromic decoding (exclude the cyclical procedure for encoding and decoding information); to reduce hardware costs for building a decoding device, since in most cases does not require hardware costs for storing error vectors; to reduce the time spent on encoding and decoding information and to ensure the operation of the data transmission channel in real time; to increase the reliability of the transmitted information by detecting uncorrectable byte errors. Thus, the proposed method for correcting errors in a given number of bytes of information with additive formation of an error vector has a regular and relatively simple procedure for constructing a code, which allows one to reduce the hardware and time costs for encoding and decoding information.