Wirelength Reduction Research Articles

A New Nonlinear Global Placement for FPGAs: The Chaotic Place

A non-linear analytical method is presented for global placement of logic cells in an IC, based on algorithms inspired in Dynamic Systems Theory, also known as Chaotic Systems. The related developed tool is called Chaotic Place. The two-dimensional structure of the cells of a circuit was obtained by the reconstruction of a Strange Attractor (Takens’ Theorem). The experiment was tested in the field programmable gate arrays (FPGAs) using the “FPGA Place-and-Route Challenge” benchmarks. For comparison of results, the Half-Perimeter-Wire-Length (HPWL) was used as the main metric. The experiment results show a 6% reduction in wirelength, on average, when compared to the state-of-the-art placement tools for homogeneous FPGAs.

Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis

The semiconductor industry has accepted three-dimensional integrated circuits (3D ICs) as a possible solution to address speed and power management problems. In addition, 3D ICs have recently demonstrated a huge potential in reducing wire length and increasing the density of a chip. However, the growing density in chips such as TSV-based 3D ICs has brought the increased temperature on chip and temperature gradients depending on location. Thus, through silicon via (TSV)-based 3D clock tree synthesis (CTS) causes thermal problems leading to large clock skew. We propose a novel 3D symmetrical buffered clock tree synthesis considering thermal variation. First, <u>3D</u> abstract tree topology based on <u>n</u>earest-<u>n</u>eighbor selection with <u>m</u>edian cost (3D-NNM) is constructed by pairing sinks that have similar power consumption. Second, the layer assignment of internal nodes is determined for uniform TSV distribution. Third, in thermal-aware 3D deferred merging embedding (DME), the exact location of TSV is determined and wire routing/buffer insertion are performed after the thermal profile based on grid is obtained. The proposed method is verified using a 45nm process technology and utilized a predictive technology model (PTM) with HSPICE. It is also evaluated for the IBM benchmarks and ISPD’09 benchmarks with no blockages. In experimental result, we achieve on average 19% of clock skew reduction compared to existing thermal-aware 3D CTS. Therefore, thermal-aware 3D symmetrical buffered clock tree synthesis presented in this work is very efficient for circuit reliability.

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs

Monolithic inter-layer vias (MIVs) used in 3D integration technology are much smaller than through-silicon vias (TSVs) used in TSV-based 3D integration. Thus, monolithic 3D integration provides shorter wire length, better performance, and lower power consumption than TSV-based 3D integration. Multi-tier monolithic 3D integration stacks more than two silicon layers, thereby increasing the device density, which reduces the wire length and power consumption and improves performance further than two-tier monolithic 3D integration. Since the size of an MIV is comparable to that of a local via, the wire lengths of multi-tier gate-level monolithic 3D IC layouts are expected to be close to the ideal wire length reduction ratio, for example, 29, 42, and 50 percent for two-, three-, and four-tier designs, respectively. However, it is still unknown whether it would be possible to achieve the ideal wire length reduction ratios by multi-tier gate-level monolithic 3D integration. In this paper, we propose an efficient routing methodology to design multi-tier monolithic 3D ICs. Using the design methodology, we design two- to eight-tier gate-level monolithic 3D IC layouts and thoroughly investigate the wire length characteristics of the layouts. The simulation results show that the proposed routing methodology reduces the wire length by 12 to 53 percent compared to the 2D designs. In addition, the proposed routing methodology builds multi-tier monolithic 3D IC layouts more efficiently than a state-of-the-art methodology with comparable routed wire length.

Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm

Nanowire field-effect transistors (NWFETs) are known to become the emerging transistor type for better performance and low power for future technology nodes beyond 7 nm. Their unique structures allow the transistors to be designed horizontally or vertically, leading to a smaller form factor. However, it is not well studied on how much improvements NWFETs can achieve, especially when vertical FETs (V-NWFETs) are invoked in designs. In this paper, we investigate the advantages that NWFETs provide to standard cell designs. We propose an interconnect structure and a design methodology that optimize design metrics such as area, wirelength, and capacitance of V-NWFET standard cells. Then, we perform comparisons on these design metrics to standard cells between FinFET, horizontal NWFET (H-NWFET), and V-NWFET. This study shows that H-NWFETs achieve significant capacitance reduction compared to the conventional FinFETs (-30.1%). In addition, V-NWFETs achieve even more capacitance reduction (-50.0%), and significant reduction in area (-22.5%) and wirelength (-14.4%) compared to FinFETs. This is possible because (1) fin-to-metal coupling consists of a significant portion in total capacitance and NWFETs contribute to the large reduction of this capacitance and (2) standard cells using V-NWFETs reduce significant area and wirelength compared to conventional FinFET standard cells. However, careful design and proper interconnect structure are required to fully exploit the design advantages.

Three-dimensional Floorplan Representations by Using Corner Links and Partial Order

Three-dimensional integrated circuit (3D IC) technology offers a potential breakthrough to enable a paradigm-shift strategy, called “more than Moore,” with novel features and advantages over the conventional 2D process technology. By having three-dimensional interconnections, 3D IC provides substantial wirelength reduction and a massive amount of bandwidth, which gives significant performance improvement to overcome many of the nontrivial challenges in semiconductor industry. Moreover, 3D integration technology enables to stack disparate technologies with various functionalities into a single system-in-package (SiP), introducing “true 3D IC” design. As the first physical design (PD) step, IC floorplanning takes a crucial role to determine IC’s overall design qualities such as footprint area, timing closure, power distribution, thermal management, and so on. However, lack of efficient 3D floorplanning algorithms that practically implement advantages of 3D integration technology is a critical bottleneck for PD automation of 3D IC design and implementation. 3D floorplanning (or packing, block partitioning) is a well-known NP-hard problem, and most of 3D floorplanning algorithms rely on heuristics and iterative improvements. Thus, developing complete and efficient 3D floorplan representations is important, since floorplan representation provides the foundation of data structure to search the solution space for 3D IC floorplanning. A well-defined floorplan representation provides a well-organized and cost-effective methodology to design high-performance 3D IC. We propose a new 3D IC floorplan representation methodology using corner links and partial order . Given a fixed number of cuboidal blocks and their volume, algorithmic 3D floorplan representations describe topological structure and physical positions/orientations of each block relative to the origin in the 3D floorplan space. In this article, (1) we introduce our novel 3D floorplan representation, called corner links representation , (2) we analyze the equivalence relation between the corner links representation and its corresponding partial order representation , and (3) we discuss several key properties of the corner links representation and partial order representation. The corner links representation provides a complete and efficient structure to assemble the original 3D mosaic floorplan. Also, the corner links representation for the non-degenerate 3D mosaic floorplan can be equivalently expressed by the four trees representation . The partial order representation defines the topological structure of the 3D floorplan with three transitive closure graphs (TCG) for each direction and captures all stitching planes in the 3D floorplan in the order of their respective directions. We demonstrate that the corner links representation can be reduced to its corresponding partial order representation, indicating that the corner links representation shares well-defined and -studied features/properties of 3D TCG-based floorplan representation. If the partial order representation describes relations between any pairs of blocks in the 3D floorplan, then the floorplan is a valid floorplan. We show that the partial order representation can restore the absolute coordinates of all blocks in the 3D mosaic floorplan by using the given physical dimensions of blocks.

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

A Novel Net Weighting Algorithm for Power and Timing-Driven Placement

Nowadays, many new low power ASICs applications have emerged. This new market trend made the designer’s task of meeting the timing and routability requirements within the power budget more challenging. One of the major sources of power consumption in modern integrated circuits (ICs) is the Interconnect. In this paper, we present a novel Power and Timing-Driven global Placement (PTDP) algorithm. Its principle is to wrap a commercial timing-driven placer with a nets weighting mechanism to calculate the nets weights based on their timing and power consumption. The new calculated weight is used to drive the placement engine to place the cells connected by the critical power or timing nets close to each other and hence reduce the parasitic capacitances of the interconnects and, by consequence, improve the timing and power consumption of the design. This approach not only improves the design power consumption but facilitates also the routability with only a minor impact on the timing closure of a few designs. The experiments carried on 40 industrial designs of different nodes, sizes, and complexities and demonstrate that the proposed algorithm is able to achieve significant improvements on Quality of Results (QoR) compared with a commercial timing driven placement flow. We effectively reduce the interconnect power by an average of 11.5% that leads to a total power improvement of 5.4%, a timing improvement of 9.4%, 13.7%, and of 3.2% in Worst Negative Slack (WNS), Total Negative Slack (TNS), and total wirelength reduction, respectively.

Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization

Given a 1-D layout with horizontal wires, cut redistribution technique is used for sliding the line-end cuts in order to merge them vertically or resolve spacing conflicts. A pair of movable cuts could have three possible relations, left-of, right-of, and merge-into. We observe that if the left-right-merge orderings of cuts are fixed, the cut redistribution can be formulated as a network flow problem, which can be solved efficiently. We also find that inserting cuts can resolve the spacing conflicts in some circumstances. According to the observations, we proposed a network-flow-based cut redistribution and insertion method for 1-D layout design. First, the orderings of the cuts are generated according to a predefined distribution. The hyperparameters of the distribution are tuned with Bayesian optimization. In order to resolve the conflicts, the cuts are redistributed and extra cuts are also inserted with network-flow-based method. Afterward, we adopt the complementary e-beam lithography to eliminate the unresolved conflicts. Finally, two wire length reduction techniques have been proposed for two different processes of e-beam, respectively. Experimental results show that compared with the existing integer linear programming-based method that does not consider the cut insertion, our method can achieve $132\times $ speedup and higher quality.

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal tradeoffs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, there are penalties associated with the serial scan design. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today’s very high-speed designs with minimum possible combinational depth, the performance degradation caused by the scan multiplexer has become magnified. Hence, to maintain circuit performance, the timing overhead of scan design must be addressed. In this paper, we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer from the functional path. The proposed design can help improve the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in the “mixed scan” test wherein it can be used as a serial scan cell as well as a random access scan (RAS) cell. The mixed scan test architecture has been implemented using the proposed scan flip-flop. The experimental results show a promising reduction in interconnect wire length, test time, and test data volume, compared to the state-of-the-art RAS and multiple serial scan implementations.

A Comparative Study of VLSI 3D Placement for power management and wirelength reduction

A Comparative Study of VLSI 3D Placement for power management and wirelength reduction

(Invited) Logic Devices for Today and Tomorrow

Half a decade ago we have witnessed a paradigm shift in CMOS technology. After more than forty years of planar device architecture serving logic industry, a need for improvement of scaling behavior of such transistors went beyond capability of traditional design knobs: dielectric thickness, supply voltage, doping of the device. Long researched FinFET transistor came to the rescue with a launch of Intel’s Ivy Bridge microprocessor in 2012. FinFET’s fully-depleted operation of thin, largely undoped body substantially surrounded by the gate, brought about significant improvement of device electrostatic behavior which led to better control of off-current while enabling better drive current at smaller gate lengths [1]. Smaller gate lengths facilitated extension of CMOS scaling into, by now, a third generation beyond last planar technology of 32nm (28nm) node. Multiple innovations assisted FinFET architecture in its scaling path, from further traditional thinning of gate’s high k dielectric and more aggressive source-drain doping engineering and buildup of stress, to self-aligned contact schemes, to thinner, straighter and taller fin profile. FinFETs are likely to afford us another node of (2D) technology scaling before being replaced by more scalable alternatives. While FinFETs have firmly been established as mainstream CMOS logic technology today, there is an alternative fully depleted device, with planar configuration, which finds itself a space in the advanced logic market. Fully-depleted planar SOI devices have less scaling potential than FinFET, however, it offers a unique device feature - back-bias – that enables post-process tunability of performance, while delivering competitive cost per wafer [2]. Nanowire, or gate-all-around (GAA) transistors, offer yet further improvements of electrostatic control of the channel that promises to extend scaling of CMOS beyond FinFETs [3]. A natural extension of FinFET geometry, horizontal nanowire (hGAA), is generally proposed in stacked configuration of 2-3 wires to make up for lesser drive current per footprint than that offered by FinFET. The potential for scaling is somewhat limited with gate length allowed to shrink by only a few nanometers for similar performance to FinFET. Transition from hGAA to vertical GAA (vGAA) devices releases this constrain. Current in vGAA flows orthogonally to wafer surface. That allows more conservative scaling of vGAA gate length and thus enables further density scaling of devices [4]. However, it does not offer improvement of drive current per footprint available to hGAA thru nanowire stacking. Careful analysis of parasitics and placement of devices in low-track-count standard cell designs will determine how much scalability will be available with GAA devices. Vertical stacking of devices (3D) provides another alternative to scaling where increased device areal density can be realized at the same design rules. A so called sequential 3D or monolithic 3D forms two or more vertically stacked tiers of devices thru transfer of blanket SOI film onto a standard wafer with fully processed devices [5]. Thickness of SOI is sufficient to maintain patterning overlay common for standard CMOS - of a few nanometers. The approach also promises improved performance thru significant reduction of interconnect wire length. Group III-V and Ge looked attractive from bulk material transport properties perspective for replacement of silicon in the channel. However, several findings about those materials suggest that they will likely not supplant silicon on CMOS scaling path. A new material, ferroelectric, applied in the structure of MOSFET gate dielectric has been shown to exhibit negative capacitance that can substantially improve device performance (both electrostatics and transport) regardless of its architecture. Those devices are known as negative capacitance FETs (NCFET) [6]. Finally we will also look at some examples of devices beyond classical drift diffusion of electrons and holes: tunnel FETs (TFET), spin-based devices and others. All have interesting features to offer with potential for niche applications. However, at this point none seems to be able to challenge Si-based technology for scaling CMOS in the next decade (Fig.1). Collaert et al, “Tall Triple-Gate Devices with TiN/HfO2 Gate Stack”, Symp. VLSI Tech. Dig., p. 108 (2005)Carter et al, “22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications”, IEDM, p.27 (2016).Jang et al., “Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node”, TED 64(6), p.2707 (2017)Yakimets et al. “Vertical GAAFETs for the Ultimate CMOS Scaling”, EDL 62(5), p.1433 (2015)Batude et al., “Advances in 3D CMOS Sequential Integration”, IEDM, p.345 (2009).H.Lee et al., “Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs“, IEDM, p.307 (2016) Figure 1

Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs

Monolithic 3-D integration is expected to provide significantly higher degree of device density than through-silicon-via-based 3-D integration due mainly to its nano-scale intertier connections. By stacking more than two device layers (multitier) within a 3-D chip, further wirelength reduction could be achieved, which can lead to additional performance and power benefits. In this paper, we propose a detailed placement algorithm called nonuniform-scaling-based placement to optimize the dynamic power consumption of multitier gate-level monolithic 3-D ICs. We also introduce delay- and length-based timing constraints to prevent potential degradation of the performance metric during placement. Under the same timing constraints, our algorithm reduces dynamic power consumption more effectively than the uniform-scaling-based placement algorithm by 2% to 14%.

Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing

The placement of cells in Integrated Circuit Design Automation has a major influence on overall design cycle. The existing popular quadratic placement techniques suffer from overlaps, large placement effort and time. In order to lower the placement overhead and to avoid the overlaps with reduced wire length, we propose a grouping and merging based placement methodology that is simpler than existing placers and easier to integrate into timing-closure flows. As a proof of concept, the proposed methodology is extensively tested on standard benchmark circuits. The proposed methodology resulted in 5× placement time reduction, 13% reduction in wire-length and 11% reduction in area with zero overlap.

GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC

Recently, there has been enormous attention given to the network on chip (NoC) because it is scalable compared to the communication bus. Three dimensional (3D) NoC is getting more popular due to the reduction of wire length with that off two dimensional NoC. The router in the NoC is provides communication between the different computational units. In this paper, a two-phase bundled-data handshake latch is used with an asynchronous router. The Mousetrap latch controller forms the basis of this asynchronous router. The major part of the arbiter is to schedule the packet, then deliver to its destination without any loss of the packet. This paper proposes a novel asynchronous 3D lottery routing algorithm which is based on arbitral mechanism. The Lottery routing algorithm distinguishes the different priorities of the input port and makes sure that it responses to the higher priority port. The proposed hardware is implemented using Cadence 180 nm technology. The result shows that the power reduction is about 17% and a slight increase in area and delay of about 2% with respect to synchronous 3D NoC.

Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits

State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

A routing framework for technology migration with bump encroachment

Technology migration plays a critical role in the time-to-market competition. Most existing works focus on layout compaction or hardware description language re-synthesis, and pay little attention to the I/O interface in flip chips. The complication of bumping process as well as electrical and reliability considerations prevent the bumps from scaling with transistor sizes. On the other hand, the number of signal bumps cannot be reduced and sometimes even increases due to the demands for wider bandwidth and various peripheral devices. As a result, the allocated die area for I/O can no longer afford the number of bumps a chip requires. This issue, known as bump encroachment, puts a stringent requirement on the redistribution layer (RDL) routing. In this paper, we first formulate the problem of RDL routing with bump encroachment, and then propose a network flow based algorithm to efficiently address it. Experimental results on a few benchmarks with parameters extracted from industrial designs show that compared with a maze routing-based approach, our algorithm can achieve up to 72% wire length reduction.

3D High Density: technology, roadmap and applications

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions. Additionally, difficulty of associating in a same 2D wafer heterogeneous processes (ie: combining Cmos device with “exotic” material, with low temperature dielectric) also gives an opportunity for a high density 3D approach rather than a 2D one. As an example, back-side illuminated imagers (BSI Imagers) players have recently released such 3D density (pitch in the range of 5 to 10 micron) [1] � From now, thinking about a 3D industrial integration within the range of few microns pitch is not anymore a dream. This specific application may raise some interest for other products such as memory denser stacking, partitioning of a large SoC � The objective of the paper is to describe 2 complementary technologies developed at CEA-Leti which address such high density of 3D integration: Hybrid Bonding in the range of few �ms; Coolcube in the range of few 100e of nms. We will first take some time to describe both technologies and recent CEA-Leti's results. The positioning of each technologies in terms of pitch and performance will be given. 1 - 3D parallel integration: hybrid bonding Hybrid bonding integration scheme has been first developed on a wafer scale approach. A test vehicle, with several BEOL layers and connected by the implementation of hybrid bonding, has been designed. Morphological and electrical data will be given leading to the conclusion that the process is very reliable and robust [1], [2]. Contact resistance per contact pads has been measured at few mOhms, which is relatively low compared to tens or even hundreds of mOhms for more classical interconnection technologies (copper pillar, bump, Cu-Cu thermos-compression). Nevertheless, for cost reason, as well as for multi dies stacking, the need for Die-To-Wafer approach remains true, while keeping a high density of interconnect [3]. The process flow as well as test vehicle designed for this approach will be described. Major challenges including handling of the dies after sawing and till the bonding itself will be addressed in the paper: wafer handler, wafer preparation and pick & place. Deep characterization is proposed. 2 - 3D sequential integration: CoolCube An alternative approach to conventional planar integration for future nodes is the monolithic 3D integration (3DVLSI). Monolithic offers the possibility to stack devices with a lithographic alignment precision enabling 3D contacts introduction at the device level (up to 100 million vias per mm� with 14nm ground rules). 3DVLSI can by routed either at gate or transistor levels. The partitioning at the gate level allows IC performance gain without resorting to scaling thanks to wire length reduction. Partitioning at the transistor level by stacking n-FET over p-FET (or the opposite) enables the independent optimization of both types of transistors (customized implementation of performance boosters: channel material / substrate orientation / channel and Raised Sources and Drains strain, etc. [4–5]) with reduced process complexity compared to a planar co-integration. The ultimate example of high performance CMOS at low process cost is the stacking of III–V nFETs above SiGe pFETs [6–7]. These high mobility transistors are well suited for 3DVLSI because their process temperatures are intrinsically low. 3DVLSI, with its high contact density, can also be seen as a powerful solution for heterogeneous co-integrations requiring high 3D vias densities such as NEMS with CMOS for gas sensing applications [8–9] or highly miniaturized imagers [10]. 3- Comparison and roadmap This paper will also provide features that give some applications' meaning for the development of both technologies in parallel. Particularly, both technologies will be compared in terms of possible pitch reachable. Main comparison features rely on advanced interconnection: dimension & pitch resistance, parasite. A thermal simulation comparison study will also be included.

Architecture of Ring-Based Redundant TSV for Clustered Faults

Three-dimensional integrated circuits (3-D-ICs) that employ the through-silicon vias (TSVs) vertically stacking multiple dies provide many benefits, such as high density, high bandwidth, and low power. However, the fabrication and bonding of TSVs may fail because of many factors, such as the winding level of the thinned wafers, the surface roughness and cleanness of silicon dies, and bonding technology. To improve the yield of 3-D-ICs, many redundant TSV (RTSV) architectures were proposed to repair 3-D-ICs with faulty TSVs. These methods reroute the signals of faulty TSVs to other regular TSV or RTSV. In practice, the faulty TSVs may cluster because of imperfect bonding technology. To resolve the problem of clustered TSV faults, router-based RTSV architecture was the first proposed to pay attention to it. Their method enables faulty TSVs to be repaired by RTSVs that are farther apart. However, to repair some rarely occurring defective patterns, their method requires too much area. In this paper, we propose a ring-based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. Assume that the size of the TSVs is 1 $\mu \text{m}$ . Simulation results show that for a given number of TSVs ( $8 \times 8$ ) and TSV failure rate (1%), our design achieves 58.9% area reduction of MUXes per signal, 54.6% total area reduction per signal, and 50.54% total wire length reduction while the yield of our ring-based RTSV architectures can still maintain 98.47%–99% as compared with the router-based design. Furthermore, the shifting length of our ring-based RTSV architecture is at most 1, which guarantees at most one MUX-delay timing overhead of each signal.