Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing

Abstract

The placement of cells in Integrated Circuit Design Automation has a major influence on overall design cycle. The existing popular quadratic placement techniques suffer from overlaps, large placement effort and time. In order to lower the placement overhead and to avoid the overlaps with reduced wire length, we propose a grouping and merging based placement methodology that is simpler than existing placers and easier to integrate into timing-closure flows. As a proof of concept, the proposed methodology is extensively tested on standard benchmark circuits. The proposed methodology resulted in 5× placement time reduction, 13% reduction in wire-length and 11% reduction in area with zero overlap.