Reduction Of Channel Length Research Articles

Modeling and characterization of low frequency noise in self-aligned top-gate coplanar IGZO thin-film transistors

Abstract A modified low-frequency noise (LFN) model was proposed to accurately estimate the quality of the gate dielectric in self-aligned top-gate (SA TG) coplanar structure indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs). The proposed LFN model was derived by modifying the conventional carrier number with correlated mobility fluctuation model considering the peculiar characteristics of SA TG coplanar IGZO TFTs such as the channel length reduction due to the diffusion of hydrogen atoms or oxygen vacancies from the source/drain to the channel, as well as the relatively large source/drain parasitic resistance. The proposed model was validated by demonstrating that the measured LFN values were in good agreement with the predicted values from the proposed model for all SA TG coplanar IGZO TFTs with SiO2 gate dielectrics deposited under different plasma-enhanced chemical vapor deposition (PECVD) power densities. The near-interface gate dielectric trap densities extracted from each TFT using the proposed LFN model revealed a clear increase as the PECVD power increased, which is considered a major cause of poor positive-bias-temperature-stress stability of the SA TG coplanar IGZO TFT with SiO2 gate dielectric deposited under high PECVD power conditions.

Elimination of cracks in Al–Zn–Mg–Cu alloy by addition of TiO2 in selective laser melting

7050 aluminium alloy is widely used in aerospace industry due to its excellent mechanical properties. 7050 aluminium alloy belongs to Al–Zn–Mg–Cu alloy. Due to the formation of cracks in selective laser melting (SLM) forming of Al–Zn–Mg–Cu alloys, 7050 aluminium alloy is difficult to be applied to forming and manufacturing in this technological field. In order to solve this critical problem, in this paper, titanium dioxide (TiO2) powder was mixed with 7050 aluminium alloy using ball milling method to achieve the effect of eliminating cracks. The cracks in the specimens completely disappeared when the TiO2 additions were 1.5 wt% and 2 wt%. With the addition of TiO2, the grains gradually changed from coarse columnar crystals to fine equiaxed crystals. Combined with the temperature field simulation, the grain refinement and crack elimination mechanism of TiO2 in SLM forming were analysed. The grain refinement is attributed to the formation of Al3Ti. The crack elimination was attributed to the reduction of the intergranular solid-liquid channel length. The maximum values of tensile strength and elongation of 7050 aluminium alloy formed by SLM are achieved at 2 wt% of TiO2. The values are 389 MPa and 8.8 %. The better mechanical properties were attributed to the synergistic effect of crack elimination, Hall-Petch, and Orowan strengthening. This study provides experimental guidance for the preparation of crack-free 7050 aluminium alloy.

Designing and performance analysis of 7 T CNTFET based novel SRAM cell for IoT application

The selection of the title includes designing of SRAM cell using CNTFET because CNTFET overcomes all the issues coming from CMOS technology beyond the 10nm technology node. With the reduction in channel length, the threshold voltage required for CMOS-based technology increases, and the corresponding off-state current decreases. This can prove to be a significant advancement for the semiconductor industry. With the evolution of the new generation of the technology era, especially beyond 10 nm, CMOS is not able to fulfil all the required conditions, as beyond 10 nm technology node, threshold voltage decreases, and consequently off-state current and leakage power increase. This is the reason that CNTFET can be considered a prominent replacement of CMOS transistor for the designing of SRAM cells with the technology node beyond 10 nm. This designed SRAM cell is applicable for IoT applications because IoT uses a microcontroller and the SRAM cell is used as a data memory in the microcontroller. A Data memory always requires high speed, ultra-low power dissipation, and high stability from the cell. Thus, to fulfil this requirement, performance analysis to identify the problem statement of conventional cells and then to improve their performance based on the findings is essential. This is the reason that the 7 T CNTFET-based SRAM novel cell is introduced, and its performance is going to be further improved so that the designed novel cell becomes compatible with IoT applications. Leakage power and stability factor are the main performance parameters to improve of SRAM cells.

Ultimate Limit in Optoelectronic Performances of Monolayer WSe2 Sloping-Channel Transistors.

Atomically thin monolayer two-dimensional (2D) semiconductors with natural immunity to short channel effects are promising candidates for sub-10 nm very large-scale integration technologies. Herein, the ultimate limit in optoelectronic performances of monolayer WSe2 field-effect transistors (FETs) is examined by constructing a sloping channel down to 6 nm. Using a simple scaling method compatible with current micro/nanofabrication technologies, we achieve a record high saturation current up to 1.3 mA/μm at room temperature, surpassing any reported monolayer 2D semiconductor transistors. Meanwhile, quasi-ballistic transport in WSe2 FETs is first demonstrated; the extracted high saturation velocity of 4.2 × 106 cm/s makes it suitable for extremely sensitive photodetectors. Furthermore, the photoresponse speed can be improved by reducing channel length due to an electric field-assisted detrapping process of photogenerated carriers in localized states. As a result, the sloping-channel device exhibits a faster response, higher detectivity, and additional polarization resolution ability compared to planar micrometer-scale devices.

P‐5: Improved Split C–V Technique for Effective Mobility Extraction in Self‐Aligned Top‐Gate Amorphous InGaZnO TFTs with Short Channel

In this paper, we evaluate the feasibility of the split capacitance‐voltage (C–V) technique for mobility extraction in self‐aligned top‐gate (SATG) amorphous InGaZnO (a‐IGZO) thin‐film transistors (TFTs) with short channel down to 5 μm. The accuracy of the effective mobility (μeff) extraction approach is greatly enhanced by properly de‐embedding the disturbances, including channel length reduction (ΔL), inner fringing capacitance (Cif), and source/drain access resistance (RSD). The results show that the parasitic bias‐dependent RSD and Cif in the inner fringe regions of the channel account for the underestimation of μeff on short‐channel devices.

Ultrascaled Contacts to Monolayer MoS2 Field Effect Transistors

Two-dimensional (2D) semiconductors possess promise for the development of field-effect transistors (FETs) at the ultimate scaling limit due to their strong gate electrostatics. However, proper FET scaling requires reduction of both channel length (LCH) and contact length (LC), the latter of which has remained a challenge due to increased current crowding at the nanoscale. Here, we investigate Au contacts to monolayer MoS2 FETs with LCH down to 100 nm and LC down to 20 nm to evaluate the impact of contact scaling on FET performance. Au contacts are found to display a ∼2.5× reduction in the ON-current, from 519 to 206 μA/μm, when LC is scaled from 300 to 20 nm. It is our belief that this study is warranted to ensure an accurate representation of contact effects at and beyond the technology nodes currently occupied by silicon.

Electrical and Optoelectrical Dual-Modulation in Perovskite-Based Vertical Field-Effect Transistors

Organolead trihalide perovskites have drawn a great deal of interest for application in electronic and optoelectronic devices owing to their exceptional physical properties. However, the majority of reported perovskite field-effect transistors (FETs) demonstrates unsatisfactory performance, such as poor mobility, low on/off ratio, and low current density, which remains a significant obstacle for their potential applications. In this work, we report a vertical FET (VFET) composed of a single-crystalline MAPbBr3 perovskite Schottky junction, which effectively modulates the intrinsic carrier characteristics and enhances the performance of the device by reducing channel length and weakening the electrostatic screening effect. The device exhibits excellent performance with a high on/off ratio (104), high carrier mobility (23.4 cm2 V–1 s–1), and current density of 2.69 A cm–2 at room temperature. Importantly, the regulation of the drain voltage plays a similar role to that of the gate voltage in our device, which is attributed to the doping of perovskite with regulation of the source contact/perovskite Schottky junction. With the drain modulation, a superior photoresponse with enhanced responsivity of 16 A W1– and a low dark current are simultaneously obtained under light illumination, leading to a high detectivity of 1014 Jones. Our research may open up new possibilities for perovskite electronics, such as logic applications for various flexible, wearable, and disposable devices.

Improvement in Short-Channel Effects of the Thin-Film Transistors Using Atomic-Layer Deposited In–Ga–Sn–O Channels With Various Channel Compositions

In–Ga–Sn–O (IGTO) thin-film transistors (TFTs) were fabricated with channel lengths from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \mu \text{m}$ </tex-math></inline-formula> to 500 nm to investigate the short-channel effects (SCEs), in which IGTO channel compositions were modulated during the atomic-layer deposition. The SCEs appearing in the IGTO TFTs were found to be manifested by increasing the In/Ga ratio of IGTO channel, showing typical channel composition dependence. Alternatively, small values of the channel-length reduction and contact resistance could be obtained to be 50 nm and 0.52 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{k}\Omega $ </tex-math></inline-formula> , respectively, for the device using the IGTO channel with an In/Ga ratio of 1.7. Threshold voltage shifts of the IGTO TFT were estimated to be only +0.03 and +1.22 V under negative and positive gate-bias stress for 104 s, respectively, even with a channel length as short as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1 \mu \text{m}$ </tex-math></inline-formula> .

Promoting hydroisomerization selectivity using channel axis reduced ZSM-48 fabricated by a combined bead-milling and porogen-assisted recrystallization method

ZSM-48 is a unidimensional zeolite that is frequently used as acid component of bi-functional hydroisomerization catalyst. As selectivity towards unwanted cracking products increases with retention time of isomerized products inside micropores, shortening their retention time inside the micropores by reducing channel length offers an effective way to improve isomerization selectivity. Direct synthesis of unidimensional zeolitic crystals with reduced channel axis is particularly difficult, since they habitually grow into rod-like shape along their channel direction. Post-synthetic bead-milling is a cost effective, mechanochemical method to decrease crystal size of zeolites from micro meter to nano meter scale, but suffers from amorphization or partial destruction of zeolitic crystals. Consequently, a post-milling recrystallization process is often entailed to remedy the destructed domains, which, nonetheless, readily causes secondary crystal growth and formation of bulky crystals that compromises the effect of bead-milling. Here, we show that porogen-assisted recrystallization can overcome the problem to fabricate channel axis reduced ZSM-48 nanocrystals. The Si/Al ratio is tunable between 30 and 200 and the acidity is largely preserved after recrystallization. The catalytic advantages of the obtained material are demonstrated in catalytic n-heptane hydroisomerization. The obtained ZSM-48 nanocrystal with Si/Al ratio of 100 outperforms the rest samples and shows enhanced isomerization yield (72% vs 62%) with respect to the parent sample. By combined diagnoses of the impact of diffusion length on product selectivity (product shape selectivity) and kinetic studies, selectivities to monomethyl branched isomers (2-methyl hexane and 3-methyl hexane) and small bulky dimethyl branched isomers (2,3- and 2,4-dimethyl pentane) are attributed to product shape selectivity, whereas the formation to bulky dimethyl branched isomers (2,2- and 3,3-dimethyl pentane) is hindered mainly by transition-state shape selectivity. The combined destructive-constructive synthetic protocol and the revelation of the origin of shape-selectivity in n-heptane hydroisomerization are useful for hydroisomerization catalyst design.

An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

&lt;p&gt;Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.&lt;/p&gt;

Influence of Reduction in Effective Channel Length on Device Operations of In-Ga-Zn-O Thin-Film Transistors With Variations in Channel Compositions

Device scaling of oxide-channel thin-film transistors (TFTs) toward sub-micrometer regime has been an urgent issue to realize higher-resolution displays and 3-D structured electronic devices. The channel-shortening effect is a serious problem in implementing the oxide TFTs with short channel lengths. In this work, the short-channel effects (SCEs) of the In-Ga-Zn-O (IGZO) TFTs were investigated with the variations in channel composition when the channel length was varied from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~\mu \text{m}$ </tex-math></inline-formula> to 500 nm. Effective channel lengths were examined to decrease with increasing the In contents, in which the reduction of the effective channel length was estimated to be 240 and 720 nm when the In/Ga ratio increased 0.7 to 1.4. The drain bias-dependent roll-offs in turn-on voltages, which typically correspond to drain-induced barrier-lowering (DIBL), also showed significant channel composition dependence. When the In/Ga ratio within the channel increased from 0.2 to 1.4, the DIBL coefficients were estimated from 22 to 244 mV/V for the devices with a channel length of 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . The channel composition-dependent variations in the effective channel length were suggested to result from the inter-diffusion and redox reactions at interfaces between the channel and electrode layers. Alternatively, the contact resistances were also examined to play major roles in determining the SCEs with scaling the devices, especially when the In contents decreased in the channel composition. Thus, properly controlling the channel composition can be concluded as such an important issue for compromising both technical strategies to reduce the channel resistance and to suppress the reduction of effective channel length.

Patent Foramen Ovale Channel Morphometric Characteristics Associated with Cryptogenic Stroke: The MorPFO Score

It is still disputable whether the specific morphologic properties of patent foramen ovale (PFO) may contribute to the occurrence of stroke. The aim of this study was to evaluate the differences in the morphometric and functional features of the PFO channel in patients with cryptogenic stroke and those without stroke. PFO channel morphology in 106 consecutive patients with cryptogenic stroke and 93 control patients without stroke with diagnosed PFO (by transesophageal echocardiography) was analyzed using transesophageal echocardiography. A validation cohort was established that consisted of 31 patients with cryptogenic stroke and 30 without stroke. Multivariable regression logistic analyses indicated PFO channel length change (odds ratio [OR], 2.50; 95% confidence interval [CI], 1.75-3.55; P<.001), PFO length/height ratio during the Valsalva maneuver (OR, 0.75; 95% CI, 0.60-0.95; P=.015), septum primum thickness (OR, 0.34; 95% CI, 0.14-0.80; P=.013), septum secundum height (OR, 0.91; 95% CI, 0.84-0.98; P=.013), the presence of an atrial septal aneurysm (OR, 3.38; 95% CI, 1.27-8.97; P=.014), and large shunt (OR, 2.49; 95% CI, 1.13-5.46; P=.022) as PFO-related stroke factors. The Morphologic Stroke Factors of PFO (MorPFO) score was developed, in which six factors were included: PFO channel length reduction (≥21%; 7 points), short septum secundum (<8.6mm; 5 points), thin septum primum (<1.6mm; 3 points), large right-to-left shunt (3 points), low PFO channel length/height ratio during the Valsalva maneuver (≤2.1; 2 points), and atrial septal aneurysm presence (1 point). Patients with scores of 0 to 7 points have low-risk PFO channels, those with scores of 8 to 11 points have intermediate-risk PFO channels, and those with scores of 12 to 21 points have high-risk PFO channels. External validation showed good MorPFO score performance (C index=0.90). Transesophageal echocardiography can be used to differentiate pathogenic from incidental PFO channels on the basis of their morphologic characteristics. The MorPFO score may help identify high-stroke-risk PFO channels.

LCE and PAMDLE Effects From Diamond Layout for MOSFETs at High-Temperature Ranges

This article presents, for the first time, a study about of behavior of the intrinsic effects from diamond layout style [longitudinal corner effect (LCE) and PArallel connection of MOSFETs with Different channel Lengths Effect (PAMDLE)] for metal–oxide–semiconductor field-effect transistors (MOSFETs) influenced by wide high-temperature ranges. These effects are capable of boosting the electrical performance of analog MOSFETs in relation to that of the standard MOSFET (rectangular gate shape). First, we have developed an experimental comparative study between MOSFETs implemented with the hexagonal layout style diamond MOSFET (DM) and its rectangular MOSFET (RM) counterpart, regarding that they present the same channel width and gate area, operating in a wide high-temperature range (from 300 to 573 K). These devices were manufactured with the technology of bulk complementary MOS (CMOS) integrated circuits (ICs) of 180 nm. The experimental results have shown that DM has obtained a better electrical performance of analog MOSFETs than the one observed in RM counterpart (for example, gains of 67% for saturation drain current and 90% for the transconductance), regardless of temperatures in which they were exposed. 3-D numerical simulations were used to justify the better electrical performance of DMs due to the LCE and PAMDLE effects, in relation to one of the RM counterparts, by observing the behavior of electrostatic potentials, longitudinal electric fields, and drain current densities of the devices as the temperature increases. Besides, a study about the short-channel effect has shown that DM can suppress this effect more effectively than RM at room temperature due to a smaller reduction in effective channel length of DM.

Key aspects affecting the performances of high-K dielectrics based single-gate and dual-gate OTFTs

The single-gate (SG) and dual-gate (DG) organic thin-film transistors (OTFTs) performances have been analyzed by using high dielectric constant material. The dielectric and gate electrode material variation does the comparative study on SG (bottom-gate bottom-contact configuration) and DG-based OTFTs. Variation in thickness of the dielectric layer (step size 2) and channel length (step size 10) results in a deviation in the performance parameters like threshold voltage, mobility, ION/IOFF current ratio, subthreshold swing, trans-conductance, etc. Such variations in the performance of OTFT have been observed by using 2D numerical devices ATLAS simulator. Subsequently, it is analyzed that reduction in channel length from 50 µm to 10 µm leads to an increase in the drain current from −9.88 × 10−10 A to −5.8 × 10−9 A (in case of DG-OTFT) and from −9.84 × 10−11 A to −5.3 × 10−9 A (in case of SG-OTFT). Similarly, the reduction in dielectric layer thickness from 10 nm to 2 nm leads to an increase in the drive current/the current ratio from 3.9 × 1012 to 1.3 × 1013 (in case of SG-OTFT) and from 1.8 × 105 to 1.5 × 106 (in case of DG-OTFT). So achieving a better result, we switch to DG- OTFT compared to SG-OTFT, which would be helpful in various future applications like chemical sensors, circuits, RFIDs, etc.

Understanding the influence of contact resistances on short-channel high-mobility organic transistors in linear and saturation regimes

Solution-processed organic field-effect transistors (OFETs) based on 2,7-didodecyl[1]benzothieno[3,2-b][1]benzothiophene (C12-BTBT) exhibit a high channel field-effect mobilities (μ FET) of 10 cm2 V−1 s−1, while effective μ FET significantly decreases with reducing channel length. Here, we investigate the influence of contact resistances on the effective μ FET of short-channel C12-BTBT FETs operated in the linear and saturation regimes. The numerical calculations using an equivalent circuit involving source and drain contact resistances reveal a large influence of the effective gate-source voltage on the reduction of saturation μ FET in short-channel OFETs. An anomalous trend in the channel-length dependence of linear and saturation μ FET in C12-BTBT FETs is also discussed.

Graphene nanoribbon field effect transistors analysis and applications

The dimension down scaling capability of the silicon based transistors has produced significant developments in the electronic industry. The channel length reduction has been accompanied by many limitations and challenges in the performance of the transistor. According to the ITRS and Moore law silicon based technology is near to its end, consequently the novel material innovations are needed in the near future. The graphene based material is the promising candidate for silicon channel replacement in conventional transistor. In this paper, graphene, graphene nanoribbons and their fundamental properties such as mechanical, electrical and electronic specifications are introduced. Then, graphene nanoribbon field effect transistor and its modeling and simulation methods are investigated. The best method for device simulation is the self-consistent solving of Poisson and Schrödinger equations under non-equilibrium green's function with the tight binding approximation. In order to investigate the effect of down scaling on the transistor performance, parameters such as drain induced barrier lowering, sub-threshold swing, ION/IOFFratio, and transconductance are studied. Moreover, utilizations of the graphene nanoribbon field effect transistor including circuit-based, high frequency, and biosensors applications are introduced. The results show that graphene based transistors are an excellent replacement to silicon based transistors.

Impact of channel length and width for charge transportation of graphene field effect transistor

The effect of channel length and width on the large and small-signal parameters of the graphene field effect transistor have been explored using an analytical approach. In the case of faster saturation as well as extremely high transit frequency, the graphene field effect transistor shows outstanding performance. From the transfer curve, it is observed that there is a positive shift of Dirac point from the voltage of 0.15 V to 0.35 V because of reducing channel length from 440 nm to 20 nm and this curve depicts that graphene shows ambipolar behavior. Besides, it is found that because of widening channel the drain current increases and the maximum current is found approximately 2.4 mA and 6 mA for channel width 2 µm and 5 µm respectively. Furthermore, an approximate symmetrical capacitance-voltage (C-V) characteristic of the graphene field effect transistor is obtained and the capacitance reduces when the channel length decreases but the capacitance can be increased by raising the channel width. In addition, a high transconductance, that demands high-speed radio frequency (RF) applications, of 6.4 mS at channel length 20 nm and 4.45 mS at channel width 5 µm along with a high transit frequency of 3.95 THz have been found that demands high-speed radio frequency applications.

Design and Fabrication Approaches of 400–600 V 4H-SiC Lateral MOSFETs for Emerging Power ICs Application

This article reports the demonstration and fabrication of 400-600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N- drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) of 5 μm, the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> of 2.5 μm and with a further reduced channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> = 0.3 μm), a record specific ON-resistance of 7.7 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400-600 V, 4H-SiC lateral MOSFETs are discussed and reported.

Effects of Channel Dimension and Doping Concentration of Source and Drain Contacts on GNRFET Performance

Growth of the electronic industry has been accompanied by the increasing number of components on a chip. Consequently, it is necessary to shrink device dimension. In this paper, effects of channel dimension reducing of the graphene nanoribbon field effect transistors (GNRFET) on performance of the GNRFET are studied. Also, effects of increasing in source/drain contacts doping concentration of the GNRFET are discussed. In order to device simulation, non-equilibrium Green’s function (NEGF) equation is applied for self-consistent solving of Poisson and Schrodinger equations with the tight binding approximation in the mode space and ballistic regime. According to the simulation results, channel length reduction of the GNRFET causes higher values in ON-state and OFF-state currents, transconductance (gm), subthreshold swing and drain induced barrier lowering (DIBL). Also, it causes lower values in threshold voltage and ION/IOFF ratio. Decreasing in channel width of the GNRFET, causes lower values in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes higher values in ION/IOFF ratio and threshold voltage. Increasing in source/drain contacts doping concentration of the GNRFET causes increasing in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes decreasing in ION/IOFF ratio and threshold voltage. The effects of channel dimension reducing and contacts doping concentration on the transistor performance should be considered for optimal design, fabrication and selection of GNRFETs in various circuits and applications.

Improving the performance of graphene nanoribbon field-effect transistors by using lanthanum aluminate as the gate dielectric

In nanoscale transistors, electron tunneling increases and causes a large leakage current due to the reduced channel length and gate oxide thickness. To reduce the short-channel effects and leakage current, the gate oxide can be selected from materials with high dielectric constant. In this paper, lanthanum aluminate (LaAlO3), a material with a high dielectric coefficient, is used as a gate dielectric in the structure of graphene nanoribbon field-effect transistors (GNRFET) and the effect of using this material on the device performance is studied. The transistor characteristics are extracted from device simulations performed by self-consistently solving the Poisson and Schrodinger equations in the nonequilibrium Green’s function formalism, employing the tight-binding approximation in the mode-space and ballistic regime. The ON-state and OFF-state currents, the ION/IOFF ratio, the threshold voltage, the drain-induced barrier lowering (DIBL), the subthreshold swing, and the transconductance (gm) are calculated for LaAlO3 as well as different materials as the gate dielectric to investigate the device performance. Based on the simulation results, the use of LaAlO3 as the gate dielectric in the transistor structure instead of other materials leads to larger values of the ON-state current, ION/IOFF ratio, and gm as well as smaller values of the OFF-state current, threshold voltage, DIBL, and subthreshold swing. According to the obtained results and excellent properties of LaAlO3, the use of this material could improve the performance of GNRFETs.