Reduced Switch Count Multilevel Inverter Research Articles

A Fifteen-Level Reduced Switch Count Multilevel Inverter with Multicarrier PWM

A multilevel inverter performs a major role in increasing the range of the level of output voltage without the use of a transformer in the power sector. Here an asymmetrical 15-level multilevel inverter fed from three unequal voltage sources has been proposed. The various modes of the conduction of the eight switches with the switching pattern are discussed with the circuit’s operation. The performance of the circuit is analysed using various techniques under MC-PWM methodologies such as Phase disposition (PD) PWM, Alternate POD (APOD) PWM, and Phase Opposition Disposition (POD) PWM. Key Finding: The logical expression used for generating the pulse pattern of the above techniques using the level shifting PWM technique to reduce the harmonics is performed, simulated, and compared by implementing three techniques for linear and non-linear load. The performance in terms of THD of output voltage under various modulation indexes is compared for various Llvel-shifting techniques. The performance of this 15L-MLI is simulated using MATLAB/Simulink and implemented in a prototype hardware model.

Design of reduced switch count multi-level inverter based electric spring for critical load voltage stability

This paper presents Transistor Clamped H-Bridge (TCHB) inverter-based Electric Spring (ES), a demand side management device that enhances the voltage stability of the critical load connected to the grid through Renewable Energy Sources (RES). This configuration of ES provides the solution to voltage sag/swell for reduced size, %THD and input power required. To validate the effectiveness of the system performance of TCHB-based ES, detailed simulation studies are performed using MATLAB/Simulink environment.

A Review of Multilevel Inverter Topologies for Grid-Connected Sustainable Solar Photovoltaic Systems

Solar energy is one of the most suggested sustainable energy sources due to its availability in nature, developments in power electronics, and global environmental concerns. A solar photovoltaic system is one example of a grid-connected application using multilevel inverters (MLIs). In grid-connected PV systems, the inverter’s design must be carefully considered to improve efficiency. The switched capacitor (SC) MLI is an appealing inverter over its alternatives for a variety of applications due to its inductor-less or transformer-less operation, enhanced voltage output, improved voltage regulation inside the capacitor itself, low cost, reduced circuit components, small size, and less electromagnetic interference. The reduced component counts are required to enhance efficiency, to increase power density, and to minimize device stress. This review presents a thorough analysis of MLIs and a classification of the existing MLI topologies, along with their merits and demerits. It also provides a detailed survey of reduced switch count multilevel inverter (RSC-MLI) topologies, including their designs, typical features, limitations, and criteria for selection. This paper also covers the survey of SC-MLI topologies with a qualitative assessment to aid in the direction of future research. Finally, this review will help engineers and researchers by providing a detailed look at the total number of power semiconductor switches, DC sources, passive elements, total standing voltage, reliability analysis, applications, challenges, and recommendations.

An improved PWM with simplified unified switched logic (USL) for RSC MLIs

ABSTRACT Inevitability to reduce the size, cost and complexity of multilevel inverter (MLI) to evolve simplified RSC (Reduced switch count) MLIs has created diversified effects such as limited switching redundancies which further restricted modularity and flexibility of implementing PWM schemes. Among the PWM schemes of RSC-MLIs, modified reduced carrier (MRC) PWM with unified switching logic (USL) is the simplest and claims to be superior with the state of art in terms of implementation, line harmonic performance, imposing least controller computational burden (of 6.5 µS to realise a three-phase seven-level RSC-MLI) by adapting minimal carrier constraints. However, this is valid for sophisticated digital controllers such as dSPACE MicroLabBox, but not for low-end cost-effective controllers such as dSPACE1104 (imposing a computational burden of nearly 25 µS to control a single-phase RSC-MLI). Thus, this paper proposes an improved USL which adopts no carrier constraints and operates with less computational burden over the conventional USL. The proposed USL gives flexibility to the user to implement a part of the switching logic with analogue circuits and thereby avoid the requirement of high-end digital controller. The scalability and superiority of the proposed USL is demonstrated for symmetrical and asymmetrical configurations of popular cascaded T-type RSC-MLI. Efficacy of the proposed USL is demonstrated with dSPACE 1104 controller and dSPACE FPGA R&D Micro-lab Box.

A novel PWM technique for reduced switch count multilevel inverter in renewable power applications

This paper described a novel pulse width modulation (PWM) technique in reduced switch count multilevel inverter (MLI) for renewable power applications. Therefore, the proposed technique finds a better solution in the multilevel inverters used for improving power quality, efficiency and reduction of switching and conduction losses. It produces a smoother sinusoidal output waveform with reduced total harmonic distortion (THD) using different modulation technique. The novel PWM technique consists of nearest level control (NLC) and level shift pulse width modulation (LSPWM). Normally semiconducting devices are added for increasing number of levels. It affects the power quality and efficiency due to losses. In this work, MLI topology with reduced number of switches count for NLC and LSPWM is presented. The single-phase and three-phase inverter configuration is used in proposed mythology. Detailed simulation results for 7-level inverter of single and three-phase inverters are presented in this paper. It is observed that NLC method is better efficiency and reduced THD than LSPWM for better utilization in renewable power applications.

A Reduced Switch Count Multilevel Inverter for PV Standalone System using Modified JAYA Algorithm

ABSTRACT This paper introduces a hybrid multilevel inverter (MLI) with reduced switch count, which can generate higher output voltage level with minimum number of DC input sources. The operation of this proposed MLI is carried out with unequal DC sources to achieve the desired output voltage level. The reduced MLI output voltage is set to minimal total harmonic distortion (THD) with the help of modified JAYA (MJAYA) algorithm. A JAYA algorithm with improved steps by adopting an accelerating parameter has been proposed in this research work to obtain a faster convergence of the objective function. The MJAYA algorithm has provided the suitable switching angles for the proposed three-phase 15-level MLI and reduced the output voltage THD to 2.23%, which satisfies the standard set by IEEE-519. To prove the efficiency of this proposed modified algorithm, the comparative analysis is carried out through MATLAB program and Simulink tool using common JAYA and modified particle swarm optimisation algorithms. The performance and productivity of the proposed MLI have been investigated through simulation and experimental setups.

A Three-Phase Reduced Switch Count Multilevel Inverter Topology

Multilevel inverters play a vital role in the industrial and renewable energy sectors due to their flexibility in synthesizing sinusoidal waveforms using a low-pass filter with a medium voltage range. It has several drawbacks, such as a higher number of power component requirements and voltage balancing problems. In this study, a new structure for multilevel inverters has been developed to offer good power quality with minimum number of switching devices and gate driver circuits. The proposed structure is configured to operate in symmetrical and asymmetrical configurations for single/three-phase versions. A simulation study using MATLAB/Simulink has been utilized to study the operating characteristics under both configurations. A laboratory prototype has been built to check the feasibility of the proposed structure for real-time applications.

Switching Sequence Control 31-Level Asymmetric Cascaded of Reduced Switch Count Multilevel Inverter with Multi Carrier Pulse Width Modulation

Various pulse width modulation techniques, including as cascaded multilevel inverters (MLI), diode clamped multilevel inverters, and flying capacitor multilevel inverters, can be used to simply operate common inverters. Due to increased switching losses, current MLIs cannot reach high efficiency. Due to lower losses and THD than standard MLI topologies, the asymmetric cascaded multi-level H-bridge inverter architecture examined in this white paper employs fewer switches and more output voltage levels (Total Harmonic Distortion). The THD is less than the IEEE standard because of the suggested architecture. In this instance, phase difference (PD) multi-carrier PWM techniques are used to control the gate pulses using sinusoidal reference. Each switch receives a different pulse pattern thanks to a method of decimal-to-binary conversion. It is possible to utilise the suggested circuit for applications requiring moderate to high power, and it is quite simple to evaluate. Utilize the MATLAB/SIMULINK environment to simulate time-domain behaviour for the 31-level and 33-level multilevel inverter topologies.

Switching Sequence Control 31-Level Asymmetric Cascaded of Reduced Switch Count Multilevel Inverter with Multi Carrier Pulse Width Modulation

Various pulse width modulation techniques, including as cascaded multilevel inverters (MLI), diode clamped multilevel inverters, and flying capacitor multilevel inverters, can be used to simply operate common inverters. Due to increased switching losses, current MLIs cannot reach high efficiency. Due to lower losses and THD than standard MLI topologies, the asymmetric cascaded multi-level H-bridge inverter architecture examined in this white paper employs fewer switches and more output voltage levels (Total Harmonic Distortion). The THD is less than the IEEE standard because of the suggested architecture. In this instance, phase difference (PD) multi-carrier PWM techniques are used to control the gate pulses using sinusoidal reference. Each switch receives a different pulse pattern thanks to a method of decimal-to-binary conversion. It is possible to utilise the suggested circuit for applications requiring moderate to high power, and it is quite simple to evaluate. Utilize the MATLAB/SIMULINK environment to simulate time-domain behaviour for the 31-level and 33-level multilevel inverter topologies.

Reduced Switch Count Multilevel Inverter with Fault Diagnosis Operation

This paper proposes a reduced switch count multilevel inverter with fault diagnosis operation to overcome the problem of a higher number of switches in a multilevel inverter and fault detection in a multilevel inverter. A multilevel inverter is a power electronic device with low switching losses and low total harmonic distortion that is used in high voltage and high power applications (THD). In a standard inverter, it’s often used to minimise the size and number of passive filters. The H-bridge topology is needed for the proposed model of reduced switch count multilevel inverter (RSC – MLI). It is used to achieve higher power ratings as well as to promote the use of renewable energy sources. It reduces switching errors and the number of power electronic switches, cost and lower order harmonics. As the number of levels and steps in the waveform increase, the harmonics in the output voltage waveform decrease, resulting in an ideal waveform that looks like a sinusoidal waveform, which reduces the harmonics at the output. Switching losses and power losses can be minimised by using a limited number of switches.

Retraction: Reduced Switch Count Multilevel Inverter with Fault Diagnosis Operation (J. Phys.: Conf. Ser. 1916 012100)

This article (and all articles in the proceedings volume relating to the same conference) has been retracted by IOP Publishing following an extensive investigation in line with the COPE guidelines. This investigation has uncovered evidence of systematic manipulation of the publication process and considerable citation manipulation.IOP Publishing respectfully requests that readers consider all work within this volume potentially unreliable, as the volume has not been through a credible peer review process.IOP Publishing regrets that our usual quality checks did not identify these issues before publication, and have since put additional measures in place to try to prevent these issues from reoccurring. IOP Publishing wishes to credit anonymous whistleblowers and the Problematic Paper Screener [1] for bringing some of the above issues to our attention, prompting us to investigate further.[1] Cabanac G, Labbé C and Magazinov A 2021 arXiv:2107.06751v1 Retraction published: 23 February 2022

A three-phase transformer based T-type topology for DSTATCOM application

ABSTRACT Among the various reduced switch count multilevel inverter (RSC-MLI) topologies, T-type is the simplified configuration with appreciable reduction in switch count and, posses an ability to serve an alternative to cascaded H-bridge (CHB) MLI. However, extreme reduction in switch count of T-type topology has limited its switching redundancies and created critical dc-link voltage balancing issues in closed-loop applications. In addition, conventional multi-reference PWM scheme reported for T-type produces poor line-voltage total harmonic distortion (THD). Therefore, in this paper, a five-level T-type topology is presented, which involves only one-third dc source requirement of conventional T-type and CHB. This will greatly reduce the dc-link voltage balancing issues and cost. Further, to improve the harmonic performance of conventional multi-reference PWM, a simple carrier-based modulation scheme is proposed. The open and closed performance on the proposed scheme is validated on Simulink and experimental environment considering five-level T-type configuration. To evaluate the dynamic performance of developed T-type configuration, a three-phase three-wire (3P3W) distributed static compensator (DSTATCOM) application is considered, where its ability to eliminate source current harmonics, reactive power and load unbalance is investigated. To promote the superiority of the developed T-type topology, its cost comparison with conventional T-type and CHB is presented.

Sliding mode controller for extraction and supply of photovoltaic power using switched series parallel sources reduced switch count multilevel inverter

The reduced switch count multilevel inverter (RSC-MLI) is the latest trend in power electronic converters due to reduction in the switch count and cost. However, a large number of RSC-MLIs have not yet reached to the application level because of the absence of modularity, unequal load-sharing among DC sources and the absence of switching redundancies. On the other hand, multilevel dc-link (MLDCL) and switched series parallel sources (SSPS) RSC-MLI topologies are modular structures with adequate switching redundancies and can be an alternative to conventional cascaded H-bridge (CHB) for grid-connected photovoltaic (PV) systems. Therefore, in this paper, a comprehensive comparison among CHB, MLDCL and SSPS topologies has been carried out for grid connected PV application. Based on the outcome, an asymmetric 11 kV three-phase 11-level SSPS RSC-MLI is chosen. In this combination, a common non-linear sliding mode controller (SMC) is developed for generating maximum PV power from asymmetric single-stage PV sources by linearizing the non-linear PV system using an effective feedback linearization scheme. The PV power extracted is delivered to the grid by controlling SSPS RSC-MLI using another SMC. The performance of the system under wide variations of insolation levels is verified in MATLAB and further validated in hardware-in-the-loop OPAL-RT controller.

A Review on Reduced Switch Count Multilevel Inverter Topologies

Multilevel Inverters (MLIs) are becoming more and more popular in medium and high power applications. This is due to several inherent advantages of MLI over two-level inverters such as high-quality output, lower device ratings, and several others. While the classical topologies are still having applications in most of the key areas, there is a growing interest in newer multilevel topologies with an objective of reducing power semiconductor device count, gate drivers and/or isolated DC sources. In this paper, a comprehensive review of some of the recently proposed newer multilevel inverter topologies with the abovementioned objectives is presented. In this article, a detailed investigation in terms of total power semiconductor switch count, number of DC sources, passive component requirement, highest switch voltage rating, total standing voltage etc. has been presented.

Logic pattern-based low-frequency pulse generation technique for modified multilevel DC-link inverters

The multilevel inverter (MLI) targets on generating a low THD output, which reduces the filter size requirement. This is achieved at the expense of increased switches, which increases the control complexity. Ongoing efforts are being made by researchers to reduce the switch count of MLIs. Many reduced switch count (RSC) topologies of MLIs have been reported in the literature along with various PWM techniques for providing the gate pulses for these topologies. The modified multilevel DC-link inverter (MMLDCLI) is one of the RSC MLI topologies, where only six switches are used to generate a seven level output. The MMLDCLI consists of series connected cells to generate a unipolar staircase waveform and a simple H-bridge acting as a polarity generator. Two unequal dc sources and six switches constitute the MMLDCLI generating a seven level output. This paper proposes a versatile gate pulse generation technique for the MMLDCLI, which enables a wide range of converter operation. This technique provides a smooth changeover in the number of output levels (5 levels/7 levels) resulting in a low THD in the output voltage. The viability and impact of the proposed technique on a MMLDCLI are analyzed through simulation and they are validated through a laboratory prototype.

Application of swarm optimisation‐based modified algorithm for selective harmonic elimination in reduced switch count multilevel inverter

Multilevel inverters (MLIs) are nowadays extensively used in integration with renewable energy sources and in drives applications. The converter cost and voltage quality improvement are the utmost importance in such application of MLI. A six-switch seven-level reduced switch symmetrical MLI (6S-7L MLI) is proposed here. Compared to the conventional and similar existing MLI topologies, the proposed MLI uses less active switches and has less driver circuit requirement. A particle swarm optimisation (PSO)-based modified selected harmonic elimination technique is derived and analysed for computing optimal switching angles of proposed 6S-7L MLI to eliminate third- and fifth-order harmonics. Moreover, the performance of the proposed algorithm is compared with the two most commonly used PSO variants. The analysis shows the modified version of PSO is most suitable for optimising the output voltage of proposed MLI through targeted harmonic elimination. The proposed topology is investigated through simulation by applying the calculated switching angles using modified PSO algorithm. Finally, a single-phase experimental prototype is designed to verify the validity of the proposed structure.

A Simplified PWM Technique for Reduced Switch Count Multilevel Inverter

<p>Penetration of multilevel inverters (MLI) in to high power and medium voltage application has been increasing because of its advantages. The conventional two levels inverter has high harmonic distortion which gives poor power quality. Lot of topologies has been developed to overcome the drawbacks of a two level inverter. These topologies include more number of switching devices which increases the design complexity and cost. The optimum design of inverter requires less number of switches with better quality in waveform. In this paper, a symmetrical five level and seven levels inverter configuration with simplified pulse width modulation technique is proposed. This proposed inverter requires less switches, less protection circuits along with low cost and size. The analysis of the inverter circuits is done by using Matlab/Simulink software. The synthesized staircase wave form is shown and total harmonic distortion (THD) is also measured.</p>

Improved pulse‐width modulation scheme for T‐type multilevel inverter

In recent times, reduced switch count multilevel inverter (RSC-MLI) has become an emerging area of research in power electronic converters. To control these RSC-MLI topologies, various novel modulation schemes are reported. Multi-reference is one of such modulation scheme reported for various RSC topologies, such as T-type. However, the performance of this conventional scheme results in high total harmonic distortion (THD) in line voltages, when compared with the conventional level shifted pulse-width modulation scheme. This observation is clearly presented in this study and the reason for its degraded THD performance has been deeply discussed. To alleviate this problem, a modified multi-reference dual-carrier modulation technique with multiple references and two carriers is proposed. To implement this proposed modulation technique, an alternate carrier and modulation signals arrangement with multiple carriers and single reference is also presented. Finally, a comparative THD performance of the proposed and conventional modulation schemes is carried out on a five-level T-type MLI and obtained simulation results are validated experimentally.

Analysis of Reduced Switch Topology Multilevel Inverter with Different Pulse Width Modulation Technique and Its Application with DSTATCOM

Multilevel inverter has played a vital role in medium and high power applications in the recent years. In this paper, Reduced Switch Count Multi Level Inverter structure (RSCMLI) topology is presented with different pulse width modulation techniques. The harmonic level analysis is carried out for the reduced switch count multilevel inverter with the different PWM technique such as with Alternate Phase Opposition Disposition (APOD) method, In Phase Disposition (IPD) method and multi reference pulse width modulation method for five level, seven level , nine level and eleven level inverter. The simulation results are compared with the cascaded H Bridge Multi Level Inverter (CHBMLI). The nine level RSCMLI inverter with APOD method is used for the Distribution Static Synchronous Compensator (DSTATCOM) application in the nonlinear load connected system for power factor improvement. The result shows that the harmonic level and the number of switches required for RSCMLI is reduced compared to CHBMLI. RSCMLI employed in DSTATCOM improves the power factor and harmonic level of the system when it is connected to the nonlinear load.

A DC-Link Capacitor Voltage Balancing with CMV Elimination Using Only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter Fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.