Logic pattern-based low-frequency pulse generation technique for modified multilevel DC-link inverters

Abstract

The multilevel inverter (MLI) targets on generating a low THD output, which reduces the filter size requirement. This is achieved at the expense of increased switches, which increases the control complexity. Ongoing efforts are being made by researchers to reduce the switch count of MLIs. Many reduced switch count (RSC) topologies of MLIs have been reported in the literature along with various PWM techniques for providing the gate pulses for these topologies. The modified multilevel DC-link inverter (MMLDCLI) is one of the RSC MLI topologies, where only six switches are used to generate a seven level output. The MMLDCLI consists of series connected cells to generate a unipolar staircase waveform and a simple H-bridge acting as a polarity generator. Two unequal dc sources and six switches constitute the MMLDCLI generating a seven level output. This paper proposes a versatile gate pulse generation technique for the MMLDCLI, which enables a wide range of converter operation. This technique provides a smooth changeover in the number of output levels (5 levels/7 levels) resulting in a low THD in the output voltage. The viability and impact of the proposed technique on a MMLDCLI are analyzed through simulation and they are validated through a laboratory prototype.