Reduced Surface Field Research Articles

Analytical Study on a 700 V Triple RESURF LDMOS With a Variable High-K Dielectric Trench

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- K (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- K (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( E-field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the N-buffer layer and P-substrate, which increases the N-buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk E-field distribution is modulated by the E-field peak generated at the position of varying K dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical E-field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON, sp</sub> than the CTR LDMOS. Moreover, the figure of merit (BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

Evaluation of Hot Carrier Impact on Lateral-DMOS with LOCOS feature

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH, ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were found to be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flicker noise assessment under the same stress shows noticeable instabilities.

Theoretical study on optimization criterion of the triple RESURF lateral power devices via virtual junction concept

The triple reduced surface field (T-RESURF) technique allows the drift region to achieve a much higher doping concentration while maintaining its breakdown voltage unaffected. Yet, as a result of the missing design guidance, the optimization of the T-RESURF effect is difficult to be realized in practice. In light of that, in this paper, the Virtual Junction Concept is proposed to provide the optimization criterion and explore physical insight of the T-RESURF effect. The proposed method bypasses the complicated 2D analysis by equivalenting the 2D drift region to a 1D virtual junction. The effectiveness and correctness of such a method are validated by the good agreement between modeled and simulated results. Benefit from its simplicity and veracity, the proposed method can not only conduct qualitative and quantitative analysis on the T-RESURF effect but also capable of providing design guidance and optimization criterion.

Modeling and Analysis of 3-D Core-Shell Superjunction Structures

Conventional superjunction (SJ) structures are composed of p- and n-type doped pillars extending longitudinally as linear stripes (LSs). The reduced surface field (RESURF) effect in these structures is essentially due to a 2-D depletion. A 3-D RESURF is expected to be better than a 2-D RESURF and may further improve the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}}$ </tex-math></inline-formula> tradeoff for SJ devices. A natural 3-D RESURF structure is a core-shell (CS) SJ structure with a cylindrical unit cell. To identify and leverage the advantages that a 3-D RESURF can offer, the CS SJ is theoretically and numerically analyzed in this article. We develop an analytical model that results in closed-form expressions for the electric field profiles in both CS and LS structures. A very close agreement is observed between the analytical results and numerical simulations. The efficacy of 2-D and 3-D RESURF is compared using the model, and it is found that neither of these designs is universally better. The superior design is determined by the fabrication technology limitations. For trench refill type technologies, the CS design can offer substantial improvement, but, for lithography limited technologies, the CS design shows a significant deterioration in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {BV}-\text {R}_{\text {DS}{(} \text {on} {)},\text {sp}} $ </tex-math></inline-formula> tradeoff compared with the LS design.

A New Split Gate Resurf Stepped Oxide UMOSFET Structure with High Doped Epitaxial Layer for Improving Figure of Merit (FOM)

The split gate resurf stepped oxide with highly doped epitaxial layer (HDSGRSO) UMOSFET has been proposed. The epitaxial layer of HDSGRSO u-shape metal oxide semiconductor field effect transistor (UMOSFET) has been divided into three parts: the upper epitaxial layer, the lower epitaxial layer and the middle epitaxial layer with higher doping concentration. The research shows that the reduced SURface field (RESURF) active has been enhanced due to the high doped epitaxial layer, which can modulate the electric field distribution and reduce the internal high electric field. Therefore, the HDGRSO UMOSFET has a higher breakdown voltage (BV), a lower on-state specific resistance (RSP) and a better figure of merit (FOM). According to the results of Technology Computer Aided Design (TCAD) simulations, the FOM (BV2/RSP) of HDSGRSO UMOSFET has been improved by 464%, and FOM (RSP × Qgd) of HDSGRSO UMOSFET has been reduced by 27.9% compared to the conventional structure, respectively, when the BV is 240 V. Furthermore, there is no extra special process required in this advanced fabrication procedure, which is relatively cost-effective and achievable.

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

Design and Fabrication Approaches of 400–600 V 4H-SiC Lateral MOSFETs for Emerging Power ICs Application

This article reports the demonstration and fabrication of 400-600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N- drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) of 5 μm, the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> of 2.5 μm and with a further reduced channel length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> = 0.3 μm), a record specific ON-resistance of 7.7 mΩ-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400-600 V, 4H-SiC lateral MOSFETs are discussed and reported.

Novel Homogenization Field Technology in Lateral Power Devices

A novel Homogenization Field Technology (HOFT) in lateral power devices is proposed and experimentally proved in this letter. By introducing the periodically discrete metal insulator semiconductor (MIS) structure, which realizes periodic equal potential and self-charge balance, the HOFT obtains almost uniform surface and bulk electric field distributions in the voltage sustaining layer. Therefore, the new device harvests both higher breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> and lower specific on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> than those of the conventional reduced surface field (RESURF) technology in much higher and wider doping dose range. The experiment of the HOFT device realized a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 672 V and a R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> of 56.7 mΩ · cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> under a high doping dose of 5.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , which represents a reduction of 33.8% when compared with the theoretical value of the triple RESURF technology.

Parasitic NPN and PNP Latch-Up Within a Single DMOS for High Voltage Reliability

This article discusses the robustness of field-plate-assisted reduced surface field effect (RESURF) DMOS designs to time-dependent latch-up within a single dielectrically isolated device. This work individually characterizes the dopant defined parasitic bipolar parallel to all MOS and uniquely describes the existence of another parasitic bipolar of opposite polarity through the generation of a backgate current as a result of weak impact ionization. These two NPN and PNP bipolar devices in a single DMOS device complete the latch-up mechanism once the product of their gains is greater than one. The characterized time-dependent nature of the increasing backgate current is accounted for by oxide charge trapping in the extended drain region, where measurements of this mechanism over a broad range of application and manufacturing variables enable a mathematical model for the time to failure to be described. Finally, the advantage of analyzing DMOS latch-up robustness in the context of individual parasitic NPN and PNP bipolar devices is shown by its ability to isolate out the separate variables feeding into each bipolar to implement robust solutions.

RESURF n-LDMOS Transistor for Advanced Integrated Circuits in 4H-SiC

The electrical behavior of lateral 4H-SiC n-laterally-diffused metal-oxide semiconductor (LDMOS) transistors with reduced surface field (RESURF) for integrated circuits was designed, measured, and modeled using different design variations. An additional implanted n-layer forming the drift region of the device in a p-doped epitaxy promotes a RESURF and thereby enhances the breakdown capability. The design rules of the presented power MOSFET are compatible to an existing technology for a novel 20-V 4H-SiC CMOS process. The dose of the additionally implanted RESURF region with a depth of approximately 390 nm was $3.5\cdot 10^{12}$ cm−2. Breakdown voltages in the range of 372–981 V and ON-state resistances from 1000 down to 54 $\text{m}\Omega $ cm2 were measured, depending on the design variations. The best measured figure-of-merit (FOM, ${V}_{{\mathrm {BD}}}^{2}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ) value results in 12.3 MW/cm2. Additionally, the electrical behavior of the presented n-LDMOS transistor was compared to a TCAD simulation model. Hereby, design guidelines concerning the length of the channel, drift region, and field plate were derived, which will be helpful for further investigations. Moreover, according to the simulations, a deeper RESURF region of $1~\mu \text{m}$ and a higher RESURF dose of $6\cdot 10^{12}$ cm−2 would even result in FOM values above 43 MW/cm2.

Guiding Principles for Trench Schottky Barrier Diodes Based on Ultrawide Bandgap Semiconductors: A Case Study in Ga₂O₃

Ultrawide bandgap (UWBG) semiconductors such as $\beta $ -Ga2O3 can support a much higher electric field than traditional wide bandgap semiconductors, thus promising an unprecedentedly low conduction loss. However, the maximum electric field in regular Schottky barrier diodes (SBDs) is limited due to the constraint set by the reverse leakage current. On the other hand, a trench SBD structure allows for a much higher electric field to be sustained thanks to the reduced surface field (RESURF) effect. In this article, the guiding principles for trench SBDs are investigated through a case study in Ga2O3. The advantages of trench SBDs are discussed both by quantitative analysis of the ON-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ), as well as by a review of the state-of-the-art Ga2O3 device performance. It is found that for kilovolt-class operation, the trench SBD structure is not only preferred but arguably necessary for high-efficiency Ga2O3 rectifiers. In addition, the effects of fin/trench geometry on the specific ON-resistance and the electric-field profile are investigated. A design flow oriented toward device performance targets is presented, together with an example design of a 1375-V Ga2O3 trench SBD, showing that a ${V}_{ \mathrm{\scriptscriptstyle ON}}$ (defined at 100 A/cm2) of below 1 V can be obtained. These results highlight the importance in harnessing the high breakdown field of UWBG semiconductors through trench SBDs for efficient power rectifiers, and provide valuable insights into the device design and optimization.

Performance enhancement of β-Ga2O3 on Si (100) based Schottky barrier diodes using REduced SURface Field

Schottky barrier diodes (SBDs) have been fabricated laterally on a β-Ga2O3 film grown on both p-type and n-type Si (100) substrates using a pulsed laser deposition technique. The sample of Ga2O3 on p-Si was further annealed at 600 °C to optimize device performance. Platinum (Pt) and Titanium (Ti)/Gold (Au) metal stacks have been utilized for the formation of Schottky and Ohmic contact on the Ga2O3, respectively. Considerably high breakdown voltages (VBR) of 190, and 172 V and a significantly low on-resistance (Ron) of 330, and 15 mΩ.cm2, have been obtained for the as-deposited sample and sample annealed at 600 °C, respectively for lateral Ga2O3/p-Si SBDs. Moreover, a much lower VBR of 56 V and higher on-resistance of 970 mΩ.cm2 have been measured for Ga2O3/n-Si SBDs as compared to the Ga2O3/p-Si. The presence of REduced SURface Field effect in n-Ga2O3/p-Si based diodes is attributed to this enhancement of its VBR as compared to n-Ga2O3/n-Si SBDs. Moreover, the highest Baliga figure of merits (V2BR/Ron) for the Ga2O3/p-Si sample annealed at 600 °C has been found to be 1.97 MW.cm−2. Thus, the present article shall open up a new power device research avenue of Ga2O3 on Si.

An innovative TCAD simulated UHV-PLDMOS device with improved HTRB performance

This study proposed an innovative TCAD simulated ultra-high voltage p-type laterally diffused metal oxide semiconductor device structure with metal II field plate optimization (metal II is the second metal used on top of metal I with 10 000 Å Oxide dielectric in between as shown in figure ), which could improve high-temperature reverse-bias (HTRB) performance. By optimizing the metal II field plate position, the exposed area could be minimized, and furthermore, after using the passivation layer of oxide-(a-Si: H)-oxide-(a-Si: H)-nitride after stress, the hole trap concentration was much lower than that in the silicon nitride and silicon dioxide passivation region because of the low mobility of (a-Si: H), which was 1 cm2 v−1 s−1. The new passivation layer maintained the original p-drift reduced surface field (RESURF) doping profile and exhibited less degradation in terms of losing positive ions from the p RESURF channel crossing oxide and entering the traps. The five layers exhibited fewer traps; therefore, the degradation was improved. The reliability of the device could be increased by changing the doping concentration of the drift region according to the RESURF principle. In addition, this study compared two passivation layers of (oxide–silicon nitride) and five passivation layers of oxide- (a-Si: H)-oxide- (a-Si: H)-nitride.

The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High-k Dielectric Pillar

The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.

High‐Breakdown‐Voltage AlGaN Channel High‐Electron‐Mobility Transistors with Reduced Surface Field Technique

In this article, reduced surface field (RESURF) AlGaN channel high‐electron‐mobility transistors (HEMTs) are proposed and investigated through 2D simulation for the first time. p+ doping is designed to form the RESURF structure, and the impact of the p+ doping density and length on breakdown characteristics is investigated. The breakdown voltage (BV) can be improved from 819 V for a conventional HEMT to 1746 V for a RESURF HEMT with a p+ doping density of 5 × 1018 cm−3 and length of 4 μm. Although the specific on‐resistance (RON) increases from 1.45 to 2.16 mΩ cm2, the power figure of merit (FOM) increases from 2.49 × 108 to 8.28 × 108 V2 Ω−1 cm−2 by utilizing a RESURF structure. By increasing the Al component of the RESURF AlGaN channel HEMT, the BV can be improved from 1746 to 2199 V. However, the RON also increases from 3.68 to 8.04 mΩ cm2, which leads to a decreasing of the power FOM. Simulation and analysis suggest that RESURF AlGaN channel HEMTs have great potential in power electronic applications.

A TCAD Study on Lateral Power MOSFET With Dual Conduction Paths and High-$k$ Passivation

A new lateral power metal-oxide-semiconductor field-effect transistor (MOSFET) with dual conduction paths and high- ${k}$ passivation is proposed. The high- ${k}$ passivation enables the dual conduction paths to realize the double reduced surface field (RESURF) action and facilitates the formation of an accumulation layer during forward conduction. The proposed device offers a 42% reduction in specific on-resistance ( ${R}_{{ON},{SP}}{)}$ when compared to a similar size baseline device with the same breakdown voltage (BV). The technology computer-aided design (TCAD) simulation results, based on a $0.5~\mu \text{m}$ bipolar-CMOS-DMOS (BCD) compatible process, show that the proposed device is able to provide a ${R}_{{ON},{SP}}$ as low as 0.28 $\text{m}\Omega \cdot $ cm2 with a BV of 92 V.

RESURF Principle in AlGaN/GaN HEMTs: Accurate 1-D Modeling on Off-State Avalanche Breakdown Behavior via Effective Concentration Profile

We present a simple but accurate 1-D methodology of modeling for AlGaN/GaN High Electron Mobility Transistors (HEMTs), and by which means study its Reduced Surface Field (RESURF) effect. By using the Effective Concentration Profile Concept, the proposed methodology accounts the interactions between each layer and electric field crowding induced by gate/drain electrodes simultaneously without introducing any simulation results and correction factors. The proposed model indicates that same as that in silicon-based lateral power devices, the RESURF effect is also present in AlGaN/GaN HEMTs. Thus, the channel layer doping of AlGaN/GaN HEMTs plays a leading role in determining the devices’ off-state characteristics. Owing to the veracity and simplicity of the proposed model, in this paper, the devices’ breakdown voltage and RESURF criterion are analytically obtained via a 1-D approach for the first time. The good agreements between the analytical model, experimental results, and 2-D simulations verify the validity of the proposed methodology.

On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs

High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Ron,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the Ron,sp is reduced, yielding a significantly improved BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Ron,sp, together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, CGD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller VDS, which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.

The differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF LDMOSFETs

AbstractThe differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF (reduced surface field) LDMOSFETs (lateral double‐diffused metal‐oxide‐semiconductor field‐effect transistors) are discussed in this paper. Two concise RESURF criteria for LDMOS with a low‐doped fully depleted N‐ buried layer (NBL) and a highly doped nondepleted N+ floating layer (NFL) are developed by optimizing the lateral and vertical electric fields. The analytical solution quantitatively demonstrates the variation of the drift charge concentration and its dependence on the key NBL and NFL parameters. It also indicates that the NBL LDMOS achieves a superior tradeoff between specific on‐resistance (Rs,on)and breakdown voltage (BV) to the NFL LDMOS. The BV2/Rs,on for NBL LDMOS is 3.1 MW/cm2, which is increased respectively by 93.8% and 40.9% compared with the single RESURF and NFL‐LDMOS.

Reliability Concerns on LDMOS With Different Split-STI Layout Patterns

Compared with the full shallow trench isolation (full-STI) lateral double-diffused MOS (LDMOS), the split-STI LDMOS has been demonstrated as a superior device with better breakdown voltage (BVOFF and specific on-resistance ( ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}})$ by virtue of its low resistance current path and dielectric reduced surface field effect. The layout of STI may not only be restricted in one pattern. Instead, it can have a variety of changes based on the split-STI structure. Actually, improvement of ${R}_{ {\scriptstyle\mathrm{ON}},\text {sp}}$ can be achieved upon modifying the STI layout pattern. In this way, four STI layout patterns, named split-STI, stair-STI, slope-STI, and H-shape-STI, are proposed. However, there is lack of information about the impacts of STI layout patterns on the reliability features of LDMOS. Therefore, in this article, the reliability features of the LDMOS with different STI layout patterns are investigated in detail, including electrical safe operating area (e-SOA), electro-static discharge (ESD) robustness, and hot carrier injection (HCI) degradation. Combining the experiment and technology computer-aided design (TCAD) simulation, the root causes of different reliability features are analyzed and discussed. Comparing them each, the LDMOS with H-shape-STI is recommended because of its better reliability features.