Reduced Surface Field Research Articles

Bottom-up vertical GaN nanocolumn Schottky barrier diodes with extremely high packing density grown by molecular beam epitaxy

In this paper, we report achieving extremely high-density packing in high-voltage vertical gallium nitride (GaN) nanocolumn Schottky barrier diodes (NC-SBDs) through the adoption of a bottom-up process. The NC-SBDs were formed via epitaxial growth using Titanium-mask selective area growth (Ti-SAG) by rf-plasma-assisted MBE (rf-MBE), realizing a packing density equivalent to exceeding 10 million columns/mm2. Our fabricated NC-SBDs with a period of 300 nm, a diameter of 250 nm, and a drift length of 1.3 μm demonstrated a breakdown voltage (BV) of 260 V with an on-resistance of 2.0 mΩcm2, yielding an excellent figure of merit of 33.8 MW/cm2 for nanocolumn-based high-voltage devices. We also discuss dielectric reduced surface field effect and impurities within the nanocolumns as potential factors contributing to the achievement of higher BV devices.

1540 V 21.8mΩ·cm2 4H-SiC lateral MOSFETs with DOUBLE RESURFs for power integration applications

This work demonstrates 4H-SiC lateral MOSFETs for power integrated circuits application designed with DOUBLE-RESURFs (reduced surface field) technology. Optimized by device simulation, the P-top RESURF dose was designed to be 10 × 1012cm−2. Various RESURF lengths (LRESURF) have been employed in the device manufacturing. As the result, the blocking capability of the fabricated device is significantly improved, and the highest breakdown voltage (BV) reaches 1540 V. Moreover, the best figure of merit (BFOM) achieved is 108 MW/cm2 with the specific ON-resistance (RON,sp) of 21.8mΩ·cm, which is competitive compared to these of reported SiC lateral MOSFETs’.

Research Progress in Breakdown Enhancement for GaN-Based High-Electron-Mobility Transistors

The breakdown characteristics are very important for GaN high-electron-mobility transistors (HEMTs), which affect the application voltage, power density, efficiency, etc. In order to further enhance the breakdown voltage of the device, it is necessary to carry out research on the breakdown mechanisms of the device. This article summarizes several breakdown mechanisms of GaN devices, including electric field concentration, buffer leakage current, gate leakage current, and vertical breakdown. In order to suppress the breakdown mechanisms, techniques such as the use of a field plate, reduced surface field (RESURF), back barrier, gate dielectric, substrate removal, and addition of AlGaN channels can be developed. With the continuous development of various technologies, the breakdown characteristics of GaN devices can be fully explored, laying the foundation for improving the performance of power electronic systems.

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plate junction electric field of 2.8 MV/cm, being close to the material limit for GaN. The device also shows a high on/off ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

A novel substrate Voltage-assisted RESURF technique in SOI LDMOS with a heavily doped drift region

A novel substrate voltage-assisted (SVA) reduced surface field (RESURF) technique in SOI lateral double-diffused Metal-Oxide-Semiconductor (LDMOS) with a heavily doped drift region is proposed. Without any additional masks and processes, an external control circuit is designed to adaptively control the substrate voltage in the technique. The co-simulation based on TCAD and the circuit is implemented to explore the mechanism of the SVA RESURF technique. In the off-state, a negative bias is applied to the substrate, which induces positive charges to compensate for the heavily doped ionizing acceptors in the drift region. The breakdown voltage is improved and remains at the same level as the conventional RESURF device. In the on-state, a zero bias is applied to the substrate, and heavy doping in the drift region can achieve low specific on-resistance compared to the RESURF device with a lightly doped drift region. As a result, the proposed technique reconstructs the charge balance and the conventional RESURF condition. The simulation results show reduced specific on-resistance, low drain leakage current, large saturation current, high transconductance and cut-off frequency, decreased turn-on/off characteristics and improved FOM and BFOM compared with the conventional RESURF technique. Furthermore, an analytical model is developed to optimize the substrate voltage for the maximum breakdown voltage in the external control circuit design of the proposed technique.

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

A novel double RESURF SOI-LIGBT with dynamic avalanche immunity and low losses

A novel, trench gates, double reduced surface field, lateral insulated gate bipolar transistor based on silicon-on-insulator (SOI-LIGBT) is proposed and investigated. A p-top layer connected to the emitter via two series diodes and n-rings surrounding the bottom of trench gates are used to reduce the on-state voltage drop (V CE(sat)) and turn-off loss (E off). A deep trench with a p-ring is introduced to form a gate-drain shorted positive channel metal oxide semiconductor, which can automatically raise the potential of the p-ring during turn-off so as to enhance the dynamic avalanche immunity. Besides, the deep trench with a p-ring can shield the high electric field from n-rings at the blocking state, which avoids the breakdown of n-rings. Simulation results indicate that the proposed LIGBT can be safely turned off even under a bus voltage equal to the breakdown voltage (V B), and V CE(sat) under E off = 1 mJ cm−2 can be 24% lower than that of the conventional LIGBT.

Implantation-free SiC thyristor with single-mask 3D termination near 10 kV

A high-voltage termination solution of junction termination extension (JTE) featuring a tapered overall profile with 3D patterned topography is proposed. This solution integrates the smoothly tapered 2D-JTE and the 3D reduced surface field concept, which improves the blocking limit in theory compared to the 2D-JTEs. Besides, this solution is implantation-free and requires only single-mask etching for fabrication, making it generally feasible for SiC bipolar devices and other wide-bandgap devices. Experiment demonstration based on SiC thyristor achieves a breakdown voltage near 10 kV (∼95% efficiency). This paper introduces its principle, methodology, and fabrication workflow.

A Two-Dimensional Model for the Field-Plate Design of High-Voltage Transistor

The field plate (FP) is a widely adopted concept and has been commonly used for high-voltage (HV) transistors to increase the breakdown voltage without enlarging the device dimension. In this article, a 2-D mathematical equation is derived for the FP design of HV transistors which reveals the potential and the electric field distributions in the reduced-surface field (RESURF) region. From the derived mathematical model, the mechanism of the FP-induced electric field suppression for the HV transistors is completely explained as the FP can reduce the potential gradient ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E} = -\nabla \varphi $ </tex-math></inline-formula> ) caused by the dielectric thickness differences above the RESURF region. The potential and the electric field distributions of the RESURF region will change as the FP is inserted due to the dielectric thickness variations. The derived equations also explained the capacitive behaviors and quantitatively described the potential and electric field distributions in different configurations of the FP-assisted RESURF devices. The results obtained by the derived equation are found to be very much accurate compared with technology computer-aided design (TCAD) simulation results.

Detailed total ionizing dose effects on LDMOS transistors

The degradation of lateral double-diffused MOSFETs (LDMOS) due to total ionizing dose (TID) effects is examined in this paper using physics-based 2D TCAD simulations. The devices under test (DUTs) are built with a single reduced surface field (single-RESURF) structure and local oxidation of silicon (LOCOS) field oxide. The device structure was chosen for its topological simplicity in comparison to other modern LDMOS transistors to explore the impact of gamma radiation on small-AC and RF behavior. The results demonstrate fundamental differences between n-type (nLDMOS) and the p-type (pLDMOS) parameter shifts. Due to the distinct damage location in the pLDMOS, which is mainly the drift region, TID augments the values of the various parasitic capacitances. However, in the nLDMOS, TID reduced those values, especially the gate capacitance overshoot, as the degradation happens in the channel region and the bird's beak mostly. Consequently, the RF response and stability of the devices will differ. In addition, we present new research opportunities for TID effects on LDMOS transistors in particular, but also for radiation studies in general.

Cold Carrier Injection Mechanism for Gate Oxide Integrity of High Voltage NDMOS

This article studies a reliability mechanism for field-plate-assisted reduced surface field (RESURF) effect 225-V NDMOS devices based on anode hole oxide injection for carriers that are in thermal equilibrium with the surrounding lattice. The injection mechanism is facilitated by a unique combination of layout and application biases that result in electric field vectors pulling low-energy minority hole carriers into oxide traps that overlap the drain potential. The effect of this positive charge trapping along the field oxide is to inhibit the RESURF mechanism, while also weakening the gate oxide where it overlaps the drain that ultimately results in a rupture. To quantify the process, a new accelerated aging technique is described that uses the parasitic n-p-n bipolar parallel of the nMOS channel to significantly increase the number of holes while still maintaining the MOS application voltages needed to enable the mechanism. This provides a cost-effective way to accurately accelerate this reliability mechanism with significantly smaller lead times relative to using higher biases and temperatures. This technique is then used with technical computer-aided design (TCAD) analysis to determine the impact of different manufacturing variables, where process controls are introduced for targeted manufacturing limits that can eliminate this mechanism from occurring.

Review of technologies for high-voltage integrated circuits

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

High-Voltage 3-D Partial SOI Technology Platform for Power Integrated Circuits

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents a PSOI technology platform with the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET),this technology achieves an ON-state resistance of 1435 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , an over 50% improvement compared with the state-of-the-art SOI technologies while maintaining competitive reliability.

A TCAD Study on High-Voltage Superjunction LDMOS with Variable-K Dielectric Trench

In this paper, a novel high voltage superjunction lateral double diffused MOSFETs (SJ-LDMOS) using a variable high permittivity (VHK) dielectric trench is presented. A relatively high HK dielectric is in the upper trench, which is connected with the drain electrode to suppress the high electric field (E-field) peak under the drain by the dielectric reduced surface field (RESURF) effect. In addition, a relatively low HK dielectric is at the bottom of the trench. On the one hand, the substrate is effectively depleted by a suitable HK dielectric layer, and the vertical depletion region of the substrate is greatly expanded. On the other hand, the overall vertical bulk E-field distribution is modulated by the E-field peaks generated at the position of varying K dielectric. A more uniform bulk E-field distribution is obtained for VHK SJ-LDMOS, leading to a high breakdown voltage (BV). Compared to the conventional SJ-LDMOS, the blocking voltage per micron of the drift region of VHK SJ-LDMOS has increased by 41.2%. Besides, compared with the SJ-LDMOS with a uniform-K, the BV of VHK SJ-LDMOS is improved by about 9.5%. The condition of the optimal range of the variable high permittivity is also presented. Meanwhile, the proposed VHK SJ-LDMOS has good conduction characteristics and heat dissipation

3-D Simulation Study of a Normally-OFF GaN Lateral Multi-Channel JFET With Optimized Electrical Field Transfer Terminal Structure

In this work, a lateral multichannel GaN-based junction field effect transistor (JFET) is proposed and studied by 3-D numerical simulation to realize normally- OFF operation and retain large output current simultaneously. Normally- OFF operation can be realized more easily due to the use of double side p-n junction gate for every single channel. We calculate the variations of the maximum saturation current and threshold voltage with channel thickness and doping concentration and obtain the corresponding transition chart from normally- ON to normally- OFF operation. Based on these optimized structure parameters, we further attempt electrical field transfer terminal technologies to improve the breakdown characteristics for the device, and we find that the drain field plate technology has much better effect than the reduced surface field technology, such that the drain field plate can transfer high electric field from the drain terminal into the insulation dielectric. The simulated breakdown voltage of the designed JFET with drain field plate reaches 880 V, leading to an increase by 50&#x0025; compared to that without drain field plate. In addition, the designed device shows a relatively high cutoff frequency up to gigahertz.

A Bulk Full-Gate SOI-LDMOS Device With Bulk Channel and Electron Accumulation Effect

A novel LDMOS featuring bulk full gate (BFG) with bulk channel and electron accumulation effect, named BFG-LDMOS, is proposed and investigated. The BFG includes bulk gate oxide (BGO) that is inserted in the ${N}$ -drift and the full gate (FG) that is formed by the wide open base transistor (P-body/ ${N}$ -drift/P + ). The gate potential is extended in the gate- ${N}$ -drift-drain (GND) region, and thus, the bulk channel of the P-body and electron accumulation effect of the ${N}$ -drift in the source- ${N}$ -drift-drain (SND) region is achieved, which significantly reduces the specific ON-resistance ( ${R}_{\text {ON,sp}}$ ). In addition, the P-body, ${N}$ -drift, and N + drain are divided by the BGO, and the P-body/ ${N}$ -drift junction (PN1) sustains the breakdown electric field for both sides, which guarantees the breakdown voltage (BV) like conventional LDMOS. The 3-D simulation results indicate that the BV and ${R}_{\text {ON,sp}}$ are 249 V and 2.93 $\text{m}\Omega \cdot $ cm 2 for the proposed BFG-LDMOS, respectively, and the Baliga’s figure of merit (FoM) is high up to 21 MW/cm 2 , which breaks through the silicon limit of the reduced surface field (RESURF).

An Efficient Automatic Structure Design Method of Silicon-on-Insulator Lateral Power Device Considering RESURF Constraint

Reduced surface field (RESURF) technology is one of the most common design optimization criteria of silicon-on-insulator (SOI) lateral power devices. This article proposes a RESURF lateral power device design method using a constrained Bayesian optimization (CBO) framework. By casting the task as a constrained optimization problem, the proposed approach can automatically generate a RESURF structure that meets given breakdown voltage (BV) and ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) specifications. The optimization scheme is equipped with two features that can improve the design quality and efficiency. First, design thresholds are used as a safety margin to further assist in reaching the target performance. Second, a model initialization sampling scheme is proposed to guide the sample selection efficiently during initialization steps. Numerical results show that the optimized designs can achieve fully depleted conditions when the breakdown occurs at N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> N junction and in the body while avoiding the p-n junction breakdown. Additionally, they also show that 1) superior designs can be achieved by introducing the design thresholds and 2) model initialization can boost the efficiency of the optimization model.

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (RON,SP) is 94 mΩmm2, and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (gm) at high gate voltages, with acceptable off-state leakage current (Ioff), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (fMAX) and cut-off frequency (fT) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

Vertical GaN-on-GaN nanowire Schottky barrier diodes by top-down fabrication approach

An optimized top-down approach was utilized to fabricate vertical GaN-on-GaN nanowire Schottky barrier diodes (NWSBDs) in this letter. The suppressed reverse leakage current and enhanced breakdown voltage (BV) of the vertical GaN NWSBDs are attributed to the reduced electric field at the interface of the Schottky junction achieved through the dielectric reduced surface field technique. As-fabricated NWSBD delivers a low turn-on voltage of 0.80 V, a near-unity ideality factor of 1.04, along with a soft BV of 480 V. The measured soft BV is comparable with the avalanche BV of the p–n diode with a similar net doping concentration in the drift region.

Design of PAMBE-based selective-area growth compliant ultra-low leakage GaN mixed-conduction vertical diodes for high-power applications * *This work was supported by the Office of Naval Research (ONR) under the ONR Award N00014-17-1-2681 (Program Manager: Lynn J Petersen).

Modern high-speed power applications require diodes with high-current capacity, larger reverse blocking voltage, lower reverse recovery transients, and lower leakage. GaN mixed-conduction vertical diodes are an attractive option for these operations. Experimentally reported GaN diodes have two major shortcomings, namely, higher leakage due to non-optimum design and conventional processing methods (e.g. ion implantation and dry etching), introducing huge leakage components. In this work, we design ultra-low leakage GaN buried p-base merged p–i–n Schottky and buried p-base merged p–i–n junction barrier controlled Schottky diodes, capable of reducing leakage current by more than five orders of magnitude by virtue of strong reduced surface field effect. Moreover, these designs are fully compliant with our earlier reported silicon nitride shadowed selective-area growth (SNS-SAG) methodology, capable of reducing the leakage by at least four orders of magnitude. In combination with SNS-SAG and highly efficient dielectric vertical sidewall edge termination scheme, these designs provide attractive options for higher performance.