Abstract
A high-voltage termination solution of junction termination extension (JTE) featuring a tapered overall profile with 3D patterned topography is proposed. This solution integrates the smoothly tapered 2D-JTE and the 3D reduced surface field concept, which improves the blocking limit in theory compared to the 2D-JTEs. Besides, this solution is implantation-free and requires only single-mask etching for fabrication, making it generally feasible for SiC bipolar devices and other wide-bandgap devices. Experiment demonstration based on SiC thyristor achieves a breakdown voltage near 10 kV (∼95% efficiency). This paper introduces its principle, methodology, and fabrication workflow.
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