Reconvergent Fanout Research Articles

Min-max timing analysis and an application to asynchronous circuits

Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper we present a 13-valued abstract waveform algebra and a polynomial-time min-max timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike several previous approaches, our algorithm computes separate propagation delay bounds from each circuit input to each internal gate. This is useful for analyzing asynchronous circuits, where the relative transition times of the inputs may not be known a priori, unlike synchronous circuits. We also describe an efficient reconvergent fanout analysis technique that helps in increasing the accuracy of simulation. We have applied our algorithm to build an efficient timing analysis tool for extended burst-mode circuits (a class of timing-dependent asynchronous circuits) implemented in the 30 design style. Our tool analyzes gate-level 30 circuits assuming bounded component delays and determines safe timing constraints for correct operation. Although our results represent conservative approximations to the true timing requirements in the worst case, experiments indicate that our technique is efficient and fairly accurate in practice.

Energy minimization using multiple supply voltages

We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling problem refers to the assignment of a supply voltage level (selected from a fixed and known number of voltage levels) to each operation in a data flow graph so as to minimize the average energy consumption for given computation time or throughput constraints or both. The energy model is accurate and accounts for the input pattern dependencies, re-convergent fanout induced dependencies, and the energy cost of level shifters. Experimental results show that using three supply voltage levels on a number of standard benchmarks, an average energy saving of 40.19% (with a computation time constraint of 1.5 times the critical path delay) can be obtained compared to using a single supply voltage level.

Comet — A new method for the deterministic test pattern generation in c-circuits

An original method (COnvergency METhod, COMET) is presented for the deterministic test pattern generation in c-circuits (combinational logic circuits), which issues a completely new theoretic approach to the Automatic Test Pattern Generation (ATPG) problem. It defines a test pattern by a pair of appropriate subgraphs (CONtrollability Graphs, CONGs) from an earlier prepared special graph (Circuit Equivalent Graph, CEG), which maps uniquely a given circuit. This new method overcomes the 5-valued logic of D-algorithm based techniques, [1–5], and is not impeded by the reconvergent fanout present in a circuit. COMET deals with single s-a-0(1) faults in the lines of a circuit. A circuit can include basic logic gates and/or single/multioutput high level modules. COMET is a descriptive method, in the sense that CONGs defining a given fault are explicitly visible on CEG. This makes the method suitable for analytical purposes, in opposition to the already existing methods which do not give the global view, with a single image, of how a test pattern is produced.

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.

Probabilistic characterization of controllability in general homogeneous circuits

A probabilistic model for the controllabilities of gates in different levels of reconvergence-free nand-gate circuits is formulated. Analytical relationships between the structural parameters (fanins) of a circuit and gate controllabilities are derived. This is achieved by characterizing the fanins of gates in a circuit using two parameters of a generalized geometric distribution. This statistical model for fanins is verified using data from well known benchmark circuits. It is shown that the behaviour of the controllabilities of gates depends on the values of the parameters of fanin distribution and the primary input controllability. Limiting values of expected controllability and rates of convergence to these limits under different conditions are presented. Further, conditions under which these results are applicable to general nand circuits (with reconvergent fanouts) are obtained. These results are extended to other homogeneous ( and, or and nor) circuits.

DLJ: A dynamic line-justification algorithm for test generation

Line justification is a basic factor in affecting the efficiency of algorithms for test generation. The existence of reconvergent fanouts in the circuit under test results in backtracks in the process of line justification. In order to reduce the number of backtracks and shorten the processing time between backtracks, we present a new algorithm called DLJ (dynamic line justification) in which two techniques are employed.1. A cost function called “FOCOST” is proposed as heuristic information to represent the cost of justifying a certain line. When the relations among the lines being justified are “and”, the line having the highest FOCOST should be chosen. When the relations are “or”, the line having the lowest FOCOST should be chosen. The computing of the FOCOST of lines is very simple. 2. Disjoint justification cubes dynamically generated to perform backtracks make the backtrack number of the algorithm minimal. When the backtrace with cubeC 1 does not yield a solution, the next cube to be chosen isC 2 ′=C 2−{C 1,C 2}. Experimental results demonstrate that the combination of the two techniques effectively reduces the backtracks and accelerates the test generation.

Probabilistic models for estimation of random and pseudo-random test length

A new probabilistic testability measure is presented to ease test length analyses of random testing and pseudorandom testing. The testability measure given in this paper is oriented to signal conflict of reconvergent fanouts. Test length analyses in this paper are based on a hard fault set, calculations of which are practicable and simple. Experimental results have been obtained to show the accuracy of this test length analyser in comparison with that of Savir[6], Chin and McCluskey[8], and Wunderlich[4] by using a pseudorandom test generator combined with exhaustive fault simulation.

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain “minimal” and “maximal” test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.

Testability measure with reconvergent fanout analysis and its applications

Many testability measure tools have been developed to reduce computational complexity of automatic test pattern generation (ATPG). These tools, by using linear algorithm or heuristics, obtain quantitative testability measure for each line within a circuit. Such testability measure is usually based on the measures of controllability and observability which do not always reflect the real situation of testability. One reason for this is that reconvergent fanouts can sometimes cause redundant faults. This paper presents a method of computing testability with reconvergent fanout checking and redundant fault detecting, while keeping a reasonable computation complexity. The result obtained is used to guide design transformations in VLSI high-level synthesis so as to generate circuits which are less costly for both ATPG and testing process.

Circuit partitioning for logic synthesis

The authors introduce a circuit partitioning method based on analysis of reconvergent fan-out. A corolla is defined as a set of overlapping reconvergent fan-out regions. The authors partition the circuit into a set of disjoint corollas and use the corollas to resynthesize the circuit. The authors develop the notion of resynthesis potential of a logic circuit and use it to select corollas that resynthesize with most gain. It is shown that resynthesis of large benchmark circuits using the corollas consistently reduces transistor pairs and layout area while improving delay and testability. The use of don't cares to further minimize the corollas in the local context and the global context is explored. >

The use of RTL descriptions in accurate timing verification and test generation (VLSI)

The authors discuss the use of high-level information in two major problems of VLSI system design: (1) accurate timing verification to eliminate false paths due to reconvergent fan-out, redundancy, and control signal constraints, and (2) testing for stuck-at-faults. The register-transfer-level (RTL) descriptions provide the set of control signals for valid data operations. Using this set of control signals, the timing verifier can perform an efficient estimation of critical path delays for only valid data transfers. This approach to critical path justification can be extended to test generation for a class of sequential circuits where all latches and memory elements can be explicitly identified. Test generation for complex VLSI circuits composed of many interconnected modules is discussed. Sequential propagation and justification of signals are carried out using the data flow information. Results based on an implementation of the algorithms are presented. >

Extended selection of switching target faults in CONT algorithm for test generation

We describe an extended selection of switching target faults in the CONT algorithm. The main difficulty in test generation is the conflict that arises in the process of determining the signal values due to reconvergent fanouts. Conventional approaches for test generation change a signal value, which causes conflicts to another possible choice for backtracking. In the CONT algorithm, a strategy of switching target fault was proposed as a new backtracking mechanism. In this method, the target fault is switched to a new target fault instead of making an alternative assignment on the primary input value when a conflict occurs. A disadvantage of the CONT algorithm is that unjustified lines exist in the process of test generation. These unjustified lines make the procedure of switching targets complicated and restrict the possible choice in selecting the new target fault. In the new version of CONT, called CONT-2, we have removed the unjustified lines in the process of test generation and have extended to two target-fault types for switching targets. Implementing CONT-2 by a Fortran program, ISCAS85 benchmark circuits are examined. Experiments on a combined system with fault simulation followed by CONT-2 are also presented.

A new model for computation of probabilistic testability in combinational circuits

Controllabilities and detectabilities for a line in a digital circuit are defined as absolute probabilities while observabilities are defined as conditional probabilities. For exact computation of these probabilities, a divide-and-conquer technique is developed in terms of subcircuits covering the original circuit. The subcircuits, called supergates, completely enclose all reconvergent fanouts. Computation of probabilities requires conditional computations within supergates with specific logical value assignments to reconvergent fanout inputs. Combining the conditional values weighted with corresponding assignment probabilities gives the total probability. Detectability computation is direct and does not require the generation of an exclusive-or function or the insertion of auxiliary gates as needed in other methods that convert the detectability problem into a controllability problem. Techniques are suggested for limiting computational effert in circuits with very large supergates where approximate computation may be desirable.

Reconvergent-fanout-oriented testability measure

This paper describes the theory and implementation of a testability measure program called RFOTM. It is suggested that the real difficulty in test generation should be reflected in testability measure. We analyse the behavior of fanout and reconvergent fanout which cause inconsistency in generating tests. A classification of fanouts is given and a class of fanouts which behaves like fanout-free lines is described. Based on this observation, the new measure is developed with emphasis on the influence of fanout and reconvergent fanout, and is shown with more accurate prediction for testing difficulty and acceptable computing complexity.

On the C-Testability of Generalized Counters

This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal arithmetic weight. These circuits consist of full and half adders interconnected in an iterative manner defined by the counting process. The general class of counter circuits contain reconvergent fanouts and are not as structurally regular as one- or two-dimensional iterative logic arrays. A model for analyzing the structure of counter circuits is proposed. Several schemes for generating test sets that exploit the iterative structure of counter circuits are presented. The testability of such circuits is enhanced by imposing certain design constraints on them. Some methods for generating easily testable counter circuits are proposed. It is shown that counter circuits can always be designed to be testable with either eight or ten tests, irrespective of the input size.

Algorithm to detect reconvergent fanouts in logic circuits

Testability measures have been advocated by many authors as aids in the designing and testing of logic circuits. These have been shown to be inaccurate for circuits which contain reconvergent fanouts. An algorithm is presented which will detect all sources of reconvergence in a circuit by processing a normal textual circuit description. As well as identifying all the gates at which reconvergence occurs, the reconvergent sites, the algorithm lists all the fanout nodes that reconverge at each of these sites. The automatic detection of reconvergence can be used for improving the testability analysis of circuits containing such fanouts. This algorithm is also being used as the basis of an analysis which identifies the undetectable faults in a circuit.

Reconvergent fanout analysis and fault simulation complexity of combinational circuits

The detectability of reconvergent fanout stem faults in a combinational logic circuit can be determined by explicitly simulating the faults within limited regions of the circuit. These regions are defined, and an estimate of the fault simulation complexity of the circuit is obtained. Results are presented for ten benchmark circuits.

An efficient algorithm for calculating Boolean difference

In this paper we have proposed a method of computing Boolean difference by means of transition operators. This method considerably simplifies the computational complexity. Particularly, when the method is used in the test generation of digital circuits, the Boolean difference can be calculated iteratively from the outputs of gates to their inputs level by level, no matter whether there are reconvergent fanout lines or not. When there are m different paths from a given fault line to the primary output of the circuit, using traditional Boolean difference methods, the result formula will contain 2m−1 product terms, whereas using the method presented in this paper, the result formula will contain onlym product terms. On the other hand, the m product terms are connected by “OR” operators, therefore it is very convenient to generate partial test patterns. We also introduce a method in which partial test patterns along a given path can be generated. The method discussed in this paper have been used in the test generation of the PCBs of several computers and the results were quite satisfactory.

Probabilistic delay evaluation in combinational digital circuits by petri nets

The present work considers the possibility of using Petri Nets (PN) as a systematic model to analyze delays in digital circuits. It has been found that PN's exhibit some interesting features in representing digital circuits at gate, element, unit or system level, whichever is needed. Furthermore, the logic verification can be achieved as a special case of the design verification because of the direct implementation of the thruth table of the circuit in the PN. In particular, a set of basic PN functions and a method of converting the circuit into the final PN, composed of the basic functions, are proposed. Moreover, an algorithm has been developed for the analysis of combinational circuits including also reconvergent fanouts and some examples are reported in the text. The algorithm may be employed to obtain the pdf of the overall circuit delay and to detect static hazards as well. The complexity of the model is directly related to that of the physical circuit to be analyzed, while the complexity of simulation does not increase with the timing precision required.

Modelling digital circuits with delays by Stochastic Petri Nets

The analysis of the behaviour of digital circuits, with special reference to signal propagation delays, is performed by means of the Petri Nets (PN) formal model. In particular, concurrent signal changes in the circuit which may give rise to possible functional errors such as races or hazards, are represented by this model. Moreover, the delays, assumed to be random variables with assigned probability distributions and Stochastic Petri Nets (SPN), which are an extension of classical PN's, are employed. By the resulting model, a great flexibility of representation is achieved, matching also the requisites of the particular technology employed. It is also possible to account for time varying inputs both in combinational and sequential circuits, reconvergent fanouts and conflicting events. The algorithm derived from this model allows to obtain a static logic verification of the circuit and exhibits shorter simulation times as compared to those of classical simulators.