Algorithm to detect reconvergent fanouts in logic circuits

Abstract

Testability measures have been advocated by many authors as aids in the designing and testing of logic circuits. These have been shown to be inaccurate for circuits which contain reconvergent fanouts. An algorithm is presented which will detect all sources of reconvergence in a circuit by processing a normal textual circuit description. As well as identifying all the gates at which reconvergence occurs, the reconvergent sites, the algorithm lists all the fanout nodes that reconverge at each of these sites. The automatic detection of reconvergence can be used for improving the testability analysis of circuits containing such fanouts. This algorithm is also being used as the basis of an analysis which identifies the undetectable faults in a circuit.